path: root/drivers/net/wireless/realtek/rtl8xxxu/regs.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
 *
 * Register definitions taken from original Realtek rtl8723au driver
 */

/* 0x0000 ~ 0x00FF	System Configuration */
#define REG_SYS_ISO_CTRL		0x0000
#define  SYS_ISO_MD2PP			BIT(0)
#define  SYS_ISO_ANALOG_IPS		BIT(5)
#define  SYS_ISO_DIOR			BIT(9)
#define  SYS_ISO_PWC_EV25V		BIT(14)
#define  SYS_ISO_PWC_EV12V		BIT(15)

#define REG_SYS_FUNC			0x0002
#define  SYS_FUNC_BBRSTB		BIT(0)
#define  SYS_FUNC_BB_GLB_RSTN		BIT(1)
#define  SYS_FUNC_USBA			BIT(2)
#define  SYS_FUNC_UPLL			BIT(3)
#define  SYS_FUNC_USBD			BIT(4)
#define  SYS_FUNC_DIO_PCIE		BIT(5)
#define  SYS_FUNC_PCIEA			BIT(6)
#define  SYS_FUNC_PPLL			BIT(7)
#define  SYS_FUNC_PCIED			BIT(8)
#define  SYS_FUNC_DIOE			BIT(9)
#define  SYS_FUNC_CPU_ENABLE		BIT(10)
#define  SYS_FUNC_DCORE			BIT(11)
#define  SYS_FUNC_ELDR			BIT(12)
#define  SYS_FUNC_DIO_RF		BIT(13)
#define  SYS_FUNC_HWPDN			BIT(14)
#define  SYS_FUNC_MREGEN		BIT(15)

#define REG_APS_FSMCO			0x0004
#define  APS_FSMCO_PFM_ALDN		BIT(1)
#define  APS_FSMCO_PFM_WOWL		BIT(3)
#define  APS_FSMCO_ENABLE_POWERDOWN	BIT(4)
#define  APS_FSMCO_MAC_ENABLE		BIT(8)
#define  APS_FSMCO_MAC_OFF		BIT(9)
#define  APS_FSMCO_SW_LPS		BIT(10)
#define  APS_FSMCO_HW_SUSPEND		BIT(11)
#define  APS_FSMCO_PCIE			BIT(12)
#define  APS_FSMCO_HW_POWERDOWN		BIT(15)
#define  APS_FSMCO_WLON_RESET		BIT(16)

#define REG_SYS_CLKR			0x0008
#define  SYS_CLK_ANAD16V_ENABLE		BIT(0)
#define  SYS_CLK_ANA8M			BIT(1)
#define  SYS_CLK_MACSLP			BIT(4)
#define  SYS_CLK_LOADER_ENABLE		BIT(5)
#define  SYS_CLK_80M_SSC_DISABLE	BIT(7)
#define  SYS_CLK_80M_SSC_ENABLE_HO	BIT(8)
#define  SYS_CLK_PHY_SSC_RSTB		BIT(9)
#define  SYS_CLK_SEC_CLK_ENABLE		BIT(10)
#define  SYS_CLK_MAC_CLK_ENABLE		BIT(11)
#define  SYS_CLK_ENABLE			BIT(12)
#define  SYS_CLK_RING_CLK_ENABLE	BIT(13)

#define REG_9346CR			0x000a
#define  EEPROM_BOOT			BIT(4)
#define  EEPROM_ENABLE			BIT(5)

#define REG_EE_VPD			0x000c
#define REG_AFE_MISC			0x0010
#define  AFE_MISC_WL_XTAL_CTRL		BIT(6)

#define REG_SPS0_CTRL			0x0011
#define REG_SPS_OCP_CFG			0x0018
#define REG_8192E_LDOV12_CTRL		0x0014
#define REG_SYS_SWR_CTRL2		0x0014
#define REG_RSV_CTRL			0x001c
#define  RSV_CTRL_WLOCK_1C		BIT(5)
#define  RSV_CTRL_DIS_PRST		BIT(6)

#define REG_RF_CTRL			0x001f
#define  RF_ENABLE			BIT(0)
#define  RF_RSTB			BIT(1)
#define  RF_SDMRSTB			BIT(2)

#define REG_LDOA15_CTRL			0x0020
#define  LDOA15_ENABLE			BIT(0)
#define  LDOA15_STANDBY			BIT(1)
#define  LDOA15_OBUF			BIT(2)
#define  LDOA15_REG_VOS			BIT(3)
#define  LDOA15_VOADJ_SHIFT		4

#define REG_LDOV12D_CTRL		0x0021
#define  LDOV12D_ENABLE			BIT(0)
#define  LDOV12D_STANDBY		BIT(1)
#define  LDOV12D_VADJ_SHIFT		4

#define REG_LDOHCI12_CTRL		0x0022

#define REG_LPLDO_CTRL			0x0023
#define  LPLDO_HSM			BIT(2)
#define  LPLDO_LSM_DIS			BIT(3)

#define REG_AFE_XTAL_CTRL		0x0024
#define  AFE_XTAL_ENABLE		BIT(0)
#define  AFE_XTAL_B_SELECT		BIT(1)
#define  AFE_XTAL_GATE_USB		BIT(8)
#define  AFE_XTAL_GATE_AFE		BIT(11)
#define  AFE_XTAL_RF_GATE		BIT(14)
#define  AFE_XTAL_GATE_DIG		BIT(17)
#define  AFE_XTAL_BT_GATE		BIT(20)

/*
 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu
 */
#define REG_AFE_PLL_CTRL		0x0028
#define  AFE_PLL_ENABLE			BIT(0)
#define  AFE_PLL_320_ENABLE		BIT(1)
#define  APE_PLL_FREF_SELECT		BIT(2)
#define  AFE_PLL_EDGE_SELECT		BIT(3)
#define  AFE_PLL_WDOGB			BIT(4)
#define  AFE_PLL_LPF_ENABLE		BIT(5)

#define REG_MAC_PHY_CTRL		0x002c

#define REG_EFUSE_CTRL			0x0030
#define REG_EFUSE_TEST			0x0034
#define  EFUSE_TRPT			BIT(7)
	/*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
#define  EFUSE_CELL_SEL			(BIT(8) | BIT(9))
#define  EFUSE_LDOE25_ENABLE		BIT(31)
#define  EFUSE_SELECT_MASK		0x0300
#define  EFUSE_WIFI_SELECT		0x0000
#define  EFUSE_BT0_SELECT		0x0100
#define  EFUSE_BT1_SELECT		0x0200
#define  EFUSE_BT2_SELECT		0x0300

#define  EFUSE_ACCESS_ENABLE		0x69	/* RTL8723 only */
#define  EFUSE_ACCESS_DISABLE		0x00	/* RTL8723 only */

#define REG_PWR_DATA			0x0038
#define  PWR_DATA_EEPRPAD_RFE_CTRL_EN	BIT(11)

#define REG_CAL_TIMER			0x003c
#define REG_ACLK_MON			0x003e
#define REG_GPIO_MUXCFG			0x0040
#define  GPIO_MUXCFG_IO_SEL_ENBT	BIT(5)
#define REG_GPIO_IO_SEL			0x0042
#define REG_MAC_PINMUX_CFG		0x0043
#define REG_GPIO_PIN_CTRL		0x0044
#define REG_GPIO_INTM			0x0048
#define  GPIO_INTM_EDGE_TRIG_IRQ	BIT(9)

#define REG_LEDCFG0			0x004c
#define  LEDCFG0_LED0CM			GENMASK(2, 0)
#define  LEDCFG0_LED1CM			GENMASK(10, 8)
#define   LED_MODE_SW_CTRL		0x0
#define   LED_MODE_TX_OR_RX_EVENTS	0x3
#define  LEDCFG0_LED0SV			BIT(3)
#define  LEDCFG0_LED1SV			BIT(11)
#define   LED_SW_OFF			0x0
#define   LED_SW_ON			0x1
#define  LEDCFG0_LED0_IO_MODE		BIT(7)
#define  LEDCFG0_LED1_IO_MODE		BIT(15)
#define   LED_IO_MODE_OUTPUT		0x0
#define   LED_IO_MODE_INPUT		0x1
#define  LEDCFG0_LED2EN			BIT(21)
#define   LED_GPIO_DISABLE		0x0
#define   LED_GPIO_ENABLE		0x1