// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AppliedMicro X-Gene Multi-purpose PHY driver
*
* Copyright (c) 2014, Applied Micro Circuits Corporation
* Author: Loc Ho <lho@apm.com>
* Tuan Phan <tphan@apm.com>
* Suman Tripathi <stripathi@apm.com>
*
* The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
* The first PLL clock macro is used for internal reference clock. The second
* PLL clock macro is used to generate the clock for the PHY. This driver
* configures the first PLL CMU, the second PLL CMU, and programs the PHY to
* operate according to the mode of operation. The first PLL CMU is only
* required if internal clock is enabled.
*
* Logical Layer Out Of HW module units:
*
* -----------------
* | Internal | |------|
* | Ref PLL CMU |----|
| 