// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
*
*/
#include <linux/module.h>
#include "pinctrl-mtk-mt8192.h"
#include "pinctrl-paris.h"
/* MT8192 have multiple bases to program pin configuration listed as the below:
* iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
* iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
* iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
* iocfg_tl:0x11F30000
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 0)
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 1)
static const struct mtk_pin_field_calc mt8192_pin_mode_range[] = {
PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8192_pin_dir_range[] = {
PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8192_pin_di_range[] = {
PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8192_pin_do_range[] = {
PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8192_pin_smt_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(1, 1, 4, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 4, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(3, 3, 4, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(4, 4, 4, 0x00f0