path: root/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Pinctrl / GPIO driver for StarFive JH7110 SoC
 *
 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
 * Copyright (C) 2022 StarFive Technology Co., Ltd.
 */

#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>

#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>

#include "../core.h"
#include "../pinctrl-utils.h"
#include "../pinmux.h"
#include "../pinconf.h"
#include "pinctrl-starfive-jh7110.h"

/* pad control bits */
#define JH7110_PADCFG_POS	BIT(7)
#define JH7110_PADCFG_SMT	BIT(6)
#define JH7110_PADCFG_SLEW	BIT(5)
#define JH7110_PADCFG_PD	BIT(4)
#define JH7110_PADCFG_PU	BIT(3)
#define JH7110_PADCFG_BIAS	(JH7110_PADCFG_PD | JH7110_PADCFG_PU)
#define JH7110_PADCFG_DS_MASK	GENMASK(2, 1)
#define JH7110_PADCFG_DS_2MA	(0U << 1)
#define JH7110_PADCFG_DS_4MA	BIT(1)
#define JH7110_PADCFG_DS_8MA	(2U << 1)
#define JH7110_PADCFG_DS_12MA	(3U << 1)
#define JH7110_PADCFG_IE	BIT(0)

/*
 * The packed pinmux values from the device tree look like this:
 *
 *  | 31 - 24 | 23 - 16 | 15 - 10 |  9 - 8   | 7 - 0 |
 *  |   din   |  dout   |  doen   | function |  pin  |
 */
static unsigned int jh7110_pinmux_din(u32 v)
{
	return (v & GENMASK(31, 24)) >> 24;
}

static u32 jh7110_pinmux_dout(u32 v)
{
	return (v & GENMASK(23, 16)) >> 16;
}

static u32 jh7110_pinmux_doen(u32 v)
{
	return (v & GENMASK(15, 10)) >> 10;
}

static u32 jh7110_pinmux_function(u32 v)
{
	return (v & GENMASK(9, 8)) >> 8;
}

static unsigned int jh7110_pinmux_pin(u32 v)
{
	return v & GENMASK(7, 0);
}

static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	return container_of(gc, struct jh7110_pinctrl, gc);
}

struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);

	return container_of(gc, struct jh7110_pinctrl, gc);
}
EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);

#ifdef CONFIG_DEBUG_FS
static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,
				struct seq_file *s, unsigned int pin)
{
	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
	const struct jh7110_pinctrl_soc_info *info = sfp->info;

	seq_printf(s, "%s", dev_name(pctldev->dev));

	if (pin < sfp->gc.ngpio) {
		unsigned int offset = 4 * (pin / 4);
		unsigned int shift  = 8 * (pin % 4);
		u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
		u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
		u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);

		dout = (dout >> shift) & info->dout_mask;
		doen = (doen >> shift) & info->doen_mask;
		gpi = ((gpi >> shift) - 2) & info->gpi_mask;

		seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
	}
}
#else
#define jh7110_pin_dbg_show NULL
#endif

static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
				 struct device_node *np,
				 struct pinctrl_map **maps,
				 unsigned int *num_maps)
{
	struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
	struct device *dev = sfp->gc.parent;
	struct device_node *child;
	struct pinctrl_map *map;
	const char **pgnames;
	const char *grpname;
	int ngroups;
	int nmaps;
	int ret;

	ngroups = 0;
	for_each_available_child_of_node(np, child)
		ngroups += 1;
	nmaps = 2 * ngroups;

	pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
	if (!pgnames)
		return -ENOMEM;

	map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
	if (!map)
		return -ENOMEM;

	nmaps = 0;
	ngroups = 0;
	mutex_lock(&sfp->mutex);
	for_each_available_child_of_node(np, child) {
		int npins = of_property_count_u32_elems(child, "pinmux");
		int *pins;
		u32 *pinmux;
		int i;

		if (npins < 1) {
			dev_err(dev,
				"invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
				np, child);
			ret = -EINVAL;
			goto put_child;
		}

		grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
		if (!grpname) {
			ret = -ENOMEM;
			goto put_child;
		}

		pgnames[ngroups++] = grpname;

		pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
		if (!pins) {
			ret = -ENOMEM;
			goto put_child;
		}

		pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
		if (!pinmux