path: root/drivers/pinctrl/zte/pinctrl-zx296718.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2017 Sanechips Technology Co., Ltd.
 * Copyright 2017 Linaro Ltd.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>

#include "pinctrl-zx.h"

#define TOP_REG0	0x00
#define TOP_REG1	0x04
#define TOP_REG2	0x08
#define TOP_REG3	0x0c
#define TOP_REG4	0x10
#define TOP_REG5	0x14
#define TOP_REG6	0x18
#define TOP_REG7	0x1c
#define TOP_REG8	0x20

/*
 * The pin numbering starts from AON pins with reserved ones included,
 * so that register data like offset and bit position for AON pins can
 * be calculated from pin number.
 */
enum zx296718_pin {
	/* aon_pmm_reg_0 */
	I2C3_SCL = 0,
	I2C3_SDA = 1,
	AON_RESERVED0 = 2,
	AON_RESERVED1 = 3,
	SEC_EN = 4,
	UART0_RXD = 5,
	UART0_TXD = 6,
	IR_IN = 7,
	SPI0_CLK = 8,
	SPI0_CS = 9,
	SPI0_TXD = 10,
	SPI0_RXD = 11,
	KEY_COL0 = 12,
	KEY_COL1 = 13,
	KEY_COL2 = 14,
	KEY_ROW0 = 15,

	/* aon_pmm_reg_1 */
	KEY_ROW1 = 16,
	KEY_ROW2 = 17,
	HDMI_SCL = 18,
	HDMI_SDA = 19,
	JTAG_TCK = 20,
	JTAG_TRSTN = 21,
	JTAG_TMS = 22,
	JTAG_TDI = 23,
	JTAG_TDO = 24,
	I2C0_SCL = 25,
	I2C0_SDA = 26,
	I2C1_SCL = 27,
	I2C1_SDA = 28,
	AON_RESERVED2 = 29,
	AON_RESERVED3 = 30,
	AON_RESERVED4 = 31,

	/* aon_pmm_reg_2 */
	SPI1_CLK = 32,
	SPI1_CS = 33,
	SPI1_TXD = 34,
	SPI1_RXD = 35,
	AON_RESERVED5 = 36,
	AON_RESERVED6 = 37,
	AUDIO_DET = 38,
	SPDIF_OUT = 39,
	HDMI_CEC = 40,
	HDMI_HPD = 41,
	GMAC_25M_OUT = 42,
	BOOT_SEL0 = 43,
	BOOT_SEL1 = 44,
	BOOT_SEL2 = 45,
	DEEP_SLEEP_OUT_N = 46,
	AON_RESERVED7 = 47,

	/* top_pmm_reg_0 */
	GMII_GTX_CLK = 48,
	GMII_TX_CLK = 49,
	GMII_TXD0 = 50,
	GMII_TXD1 = 51,
	GMII_TXD2 = 52,
	GMII_TXD3 = 53,
	GMII_TXD4 = 54,
	GMII_TXD5 = 55,
	GMII_TXD6 = 56,
	GMII_TXD7 = 57,
	GMII_TX_ER = 58,
	GMII_TX_EN = 59,
	GMII_RX_CLK = 60,
	GMII_RXD0 = 61,
	GMII_RXD1 = 62,
	GMII_RXD2 = 63,

	/* top_pmm_reg_1 */
	GMII_RXD3 = 64,
	GMII_RXD4 = 65,
	GMII_RXD5 = 66,
	GMII_RXD6 = 67,
	GMII_RXD7 = 68,
	GMII_RX_ER = 69,
	GMII_RX_DV = 70,
	GMII_COL = 71,
	GMII_CRS = 72,
	GMII_MDC = 73,
	GMII_MDIO = 74,
	SDIO1_CLK = 75,
	SDIO1_CMD = 76,
	SDIO1_DATA0 = 77,
	SDIO1_DATA1 = 78,
	SDIO1_DATA2 = 79,

	/* top_pmm_reg_2 */
	SDIO1_DATA3 = 80,
	SDIO1_CD = 81,
	SDIO1_WP = 82,
	USIM1_CD = 83,
	USIM1_CLK = 84,
	USIM1_RST = 85,

	/* top_pmm_reg_3 */
	USIM1_DATA = 86,
	SDIO0_CLK = 87,
	SDIO0_CMD = 88,
	SDIO0_DATA0 = 89,
	SDIO0_DATA1 = 90,
	SDIO0_DATA2 = 91,
	SDIO0_DATA3 = 92,
	SDIO0_CD = 93,
	SDIO0_WP = 94,

	/* top_pmm_reg_4 */
	TSI0_DATA0 = 95,
	SPINOR_CLK = 96,
	TSI2_DATA = 97,
	TSI2_CLK = 98,
	TSI2_SYNC = 99,
	TSI2_VALID = 100,
	SPINOR_CS = 101,
	SPINOR_DQ0 = 102,
	SPINOR_DQ1 = 103,
	SPINOR_DQ2 = 104,
	SPINOR_DQ3 = 105,
	VGA_HS = 106,
	VGA_VS = 107,
	TSI3_DATA = 108,

	/* top_pmm_reg_5 */
	TSI3_CLK = 109,
	TSI3_SYNC = 110,
	TSI3_VALID = 111,
	I2S1_WS = 112,
	I2S1_BCLK = 113,
	I2S1_MCLK = 114,
	I2S1_DIN0 = 115,
	I2S1_DOUT0 = 116,
	SPI3_CLK = 117,
	SPI3_CS = 118,
	SPI3_TXD = 119,
	NAND_LDO_MS18_SEL = 120,

	/* top_pmm_reg_6 */
	SPI3_RXD = 121,
	I2S0_MCLK = 122,
	I2S0_BCLK = 123,
	I2S0_WS = 124,
	I2S0_DIN0 = 125,
	I2S0_DOUT0 = 126,
	I2C5_SCL = 127,
	I2C5_SDA = 128,
	SPI2_CLK = 129,
	SPI2_CS = 130,
	SPI2_TXD = 131,

	/* top_pmm_reg_7 */
	SPI2_RXD = 132,
	NAND_WP_N = 133,
	NAND_PAGE_SIZE0 = 134,
	NAND_PAGE_SIZE1 = 135,
	NAND_ADDR_CYCLE = 136,
	NAND_RB0 = 137,
	NAND_RB1 = 138,
	NAND_RB2 = 139,
	NAND_RB3 = 140,

	/* top_pmm_reg_8 */
	GMAC_125M_IN = 141,
	GMAC_50M_OUT = 142,
	SPINOR_SSCLK_LOOPBACK = 143,
	SPINOR_SDIO1CLK_LOOPBACK = 144,
};

static const struct pinctrl_pin_desc zx296718_pins[] = {
	/* aon_pmm_reg_0 */
	AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
		AON_MUX(0x0, "ANMI"),		/* anmi */
		AON_MUX(0x1, "AGPIO"),		/* agpio29 */
		AON_MUX(0x2, "nonAON"),		/* pin0 */
		AON_MUX(0x3, "EXT_INT"),	/* int4 */
		TOP_MUX(0x0, "I2C3"),		/* scl */
		TOP_MUX(0x1, "SPI2"),		/* txd */
		TOP_MUX(0x2, "I2S1")),		/* din0 */
	AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
		AON_MUX(0x0, "WD"),		/* rst_b */
		AON_MUX(0x1, "AGPIO"),		/* agpio30 */
		AON_MUX(0x2, "nonAON"),		/* pin1 */
		AON_MUX(0x3, "EXT_INT"),	/* int5 */
		TOP_MUX(