path: root/drivers/platform/x86/amd/pmf/pmf.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * AMD Platform Management Framework Driver
 *
 * Copyright (c) 2022, Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
 */

#ifndef PMF_H
#define PMF_H

#include <linux/acpi.h>
#include <linux/input.h>
#include <linux/platform_profile.h>

#define POLICY_BUF_MAX_SZ		0x4b000
#define POLICY_SIGN_COOKIE		0x31535024
#define POLICY_COOKIE_OFFSET		0x10

/* List of supported CPU ids */
#define AMD_CPU_ID_RMB                  0x14b5
#define AMD_CPU_ID_PS                   0x14e8
#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122

struct cookie_header {
	u32 sign;
	u32 length;
} __packed;

/* APMF Functions */
#define APMF_FUNC_VERIFY_INTERFACE			0
#define APMF_FUNC_GET_SYS_PARAMS			1
#define APMF_FUNC_SBIOS_REQUESTS			2
#define APMF_FUNC_SBIOS_HEARTBEAT			4
#define APMF_FUNC_AUTO_MODE					5
#define APMF_FUNC_SET_FAN_IDX				7
#define APMF_FUNC_OS_POWER_SLIDER_UPDATE		8
#define APMF_FUNC_STATIC_SLIDER_GRANULAR       9
#define APMF_FUNC_DYN_SLIDER_AC				11
#define APMF_FUNC_DYN_SLIDER_DC				12
#define APMF_FUNC_NOTIFY_SMART_PC_UPDATES		14
#define APMF_FUNC_SBIOS_HEARTBEAT_V2			16

/* Message Definitions */
#define SET_SPL				0x03 /* SPL: Sustained Power Limit */
#define SET_SPPT			0x05 /* SPPT: Slow Package Power Tracking */
#define SET_FPPT			0x07 /* FPPT: Fast Package Power Tracking */
#define GET_SPL				0x0B
#define GET_SPPT			0x0D
#define GET_FPPT			0x0F
#define SET_DRAM_ADDR_HIGH	0x14
#define SET_DRAM_ADDR_LOW	0x15
#define SET_TRANSFER_TABLE	0x16
#define SET_STT_MIN_LIMIT	0x18 /* STT: Skin Temperature Tracking */
#define SET_STT_LIMIT_APU	0x19
#define SET_STT_LIMIT_HS2	0x1A
#define SET_SPPT_APU_ONLY	0x1D
#define GET_SPPT_APU_ONLY	0x1E
#define GET_STT_MIN_LIMIT	0x1F
#define GET_STT_LIMIT_APU	0x20
#define GET_STT_LIMIT_HS2	0x21
#define SET_P3T				0x23 /* P3T: Peak Package Power Limit */
#define SET_PMF_PPT            0x25
#define SET_PMF_PPT_APU_ONLY   0x26

/* OS slider update notification */
#define DC_BEST_PERF		0
#define DC_BETTER_PERF		1
#define DC_BATTERY_SAVER	3
#define AC_BEST_PERF		4
#define AC_BETTER_PERF		5
#define AC_BETTER_BATTERY	6

/* Fan Index for Auto Mode */
#define FAN_INDEX_AUTO		0xFFFFFFFF

#define ARG_NONE 0
#define AVG_SAMPLE_SIZE 3

/* Policy Actions */
#define PMF_POLICY_SPL						2
#define PMF_POLICY_SPPT						3
#define PMF_POLICY_FPPT						4
#define PMF_POLICY_SPPT_APU_ONLY				5
#define PMF_POLICY_STT_MIN					6
#define PMF_POLICY_STT_SKINTEMP_APU				7
#define PMF_POLICY_STT_SKINTEMP_HS2				8
#define PMF_POLICY_SYSTEM_STATE					9
#define PMF_POLICY_BIOS_OUTPUT_1				10
#define PMF_POLICY_BIOS_OUTPUT_2				11
#define PMF_POLICY_P3T						38
#define PMF_POLICY_BIOS_OUTPUT_3				57
#define PMF_POLICY_BIOS_OUTPUT_4				58
#define PMF_POLICY_BIOS_OUTPUT_5				59
#define PMF_POLICY_BIOS_OUTPUT_6				60
#define PMF_POLICY_BIOS_OUTPUT_7				61
#define PMF_POLICY_BIOS_OUTPUT_8				62
#define PMF_POLICY_BIOS_OUTPUT_9				63
#define PMF_POLICY_BIOS_OUTPUT_10				64

/* TA macros */
#define PMF_TA_IF_VERSION_MAJOR				1
#define TA_PMF_ACTION_MAX					32
#define TA_PMF_UNDO_MAX						8
#define TA_OUTPUT_RESERVED_MEM				906
#define MAX_OPERATION_PARAMS					4

#define PMF_IF_V1		1
#define PMF_IF_V2		2

#define APTS_MAX_STATES		16

/* APTS PMF BIOS Interface */
struct amd_pmf_apts_output {
	u16 table_version;
	u32 fan_table_idx;
	u32 pmf_ppt;
	u32 ppt_pmf_apu_only;
	u32 stt_min_limit;
	u8 stt_skin_temp_limit_apu;
	u8 stt_skin_temp_limit_hs2;
} __packed;

struct amd_pmf_apts_granular_output {
	u16 size;
	struct amd_pmf_apts_output val;
} __packed;

struct amd_pmf_apts_granular {
	u16 size;
	struct amd_pmf_apts_output val[APTS_MAX_STATES];
};

struct sbios_hb_event_v2 {
	u16 size;
	u8 load;
	u8 unload;
	u8 suspend;
	u8 resume;
} __packed;

enum sbios_hb_v2 {
	ON_LOAD,
	ON_UNLOAD,
	ON_SUSPEND,
	ON_RESUME,
};

/* AMD PMF BIOS interfaces */
struct apmf_verify_interface {
	u16 size;
	u16 version;
	u32 notification_mask;
	u32 supported_functions;
} __packed;

struct apmf_system_params {
	u16 size;
	u32 valid_mask;
	u32 flags;
	u8 command_code;
	u32 heartbeat_int;
} __packed;

struct apmf_sbios_req {
	u16 size;
	u32 pending_req;
	u8 rsd;
	u8 cql_event;
	u8 amt_event;
	u32 fppt;
	u32 sppt;
	u32 fppt_apu_only;
	u32 spl;
	u32 stt_min_limit;
	u8 skin_temp_apu;
	u8 skin_temp_hs2;
} __packed;

struct apmf_sbios_req_v2 {
	u16 size;
	u32 pending_req;
	u8 rsd;
	u32 ppt_pmf;
	u32 ppt_pmf_apu_only;
	u32 stt_min_limit;
	u8 skin_temp_apu;
	u8 skin_temp_hs2;
	u32 custom_policy[10];
} __packed;

struct apmf_fan_idx {
	u16 size;
	u8 fan_ctl_mode;
	u32 fan_ctl_idx;
} __packed;

struct smu_pmf_metrics_v2 {
	u16 core_frequency[16];		/* MHz */
	u16 core_power[16];		/* mW */
	u16 core_temp[16];		/* centi-C */
	u16 gfx_temp;			/* centi-C */
	u16 soc_temp;			/* centi-C */
	u16 stapm_opn_limit;		/* mW */
	u16 stapm_cur_limit;		/* mW */
	u16 infra_cpu_maxfreq;		/* MHz */
	u16 infra_gfx_maxfreq;		/* MHz */
	u16 skin_temp;			/* centi-C */
	u16 gfxclk_freq;		/* MHz */
	u16 fclk_freq;			/* MHz */
	u16 gfx_activity;		/* GFX busy % [0-100] */
	u16 socclk_freq;		/* MHz */
	u16 vclk_freq;			/* MHz */
	u16 vcn_activity;		/* VCN busy % [0-100] */
	u16 vpeclk_freq;		/* MHz */
	u16 ipuclk_freq;		/* MHz */
	u16 ipu_busy[8];		/* NPU busy % [0-100] */
	u16 dram_reads;			/* MB/sec */
	u16 dram_writes;		/* MB/sec */
	u16 core_c0residency[16];	/* C0 residency % [0-100] */
	u16 ipu_power;			/* mW */
	u32 apu_power;			/* mW */
	u32 gfx_power;			/* mW */
	u32 dgpu_power;			/* mW */
	u32 socket_power;		/* mW */
	u32 all_core_power;		/* mW */
	u32 filter_alpha_value;		/* time constant [us] */
	u32 metrics_counter;
	u16 memclk_freq;		/* MHz */
	u16 mpipuclk_freq;		/* MHz */
	u16 ipu_reads;			/* MB/sec */
	u16 ipu_writes;			/* MB/sec */
	u32 throttle_residency_prochot;
	u32 throttle_residency_spl;
	u32 throttle_residency_fppt;
	u32 throttle_residency_sppt;
	u32 throttle_residency_thm_core;
	u32 throttle_residency_thm_gfx;
	u32 throttle_residency_thm_soc;
	u16 psys;
	u16 spare1;
	u32 spare[6];
} __packed;

struct smu_pmf_metrics {
	u16 gfxclk_freq; /* in MHz */
	u16 socclk_freq; /* in MHz */
	u16 vclk_freq; /* in MHz */
	u16 dclk_freq; /* in MHz */
	u16 memclk_freq; /* in MHz */
	u16 spare;
	u16 gfx_activity; /* in Centi */
	u16 uvd_activity; /* in Centi */
	u16 voltage[2]; /* in mV */
	u16 currents[2]; /* in mA */
	u16 power[2];/* in mW */
	u16 core_freq[8]; /* in MHz */
	u16 core_power[8]; /* in mW */
	u16 core_temp[8]; /* in centi-Celsius */
	u16 l3_freq; /* in MHz */
	u16 l3_temp; /* in centi-Celsius */
	u16 gfx_temp; /* in centi-Celsius */
	u16 soc_temp; /* in centi-Celsius */
	u16 throttler_status;
	u16 current_socketpower; /* in mW */
	u16 stapm_orig_limit; /* in W */
	u16 stapm_cur_limit; /* in W */
	u32 apu_power; /* in mW */
	u32 dgpu_power; /* in mW */
	u16 vdd_tdc_val; /* in mA */
	u16 soc_tdc_val; /* in mA */
	u16 vdd_edc_val; /* in mA */
	u16 soc_edcv_al; /* in mA */
	u16 infra_cpu_maxfreq; /* in MHz */
	u16 infra_gfx_maxfreq; /* in MHz */
	u16 skin_temp; /* in centi-Celsius */
	u16 device_state;
	u16 curtemp; /* in centi-Celsius */
	u16 filter_alpha_value;
	u16 avg_gfx_clkfrequency;
	u16 avg_fclk_frequency;
	u16 avg_gfx_activity;
	u16 avg_socclk_frequency;
	u16 avg_vclk_frequency;
	u16 avg_vcn_activity;
	u16 avg_dram_reads;
	u16 avg_dram_writes;
	u16 avg_socket_power;
	u16 avg_core_power[2];
	u16 avg_core_c0residency[16];
	u16 spare1;
	u32 metrics_counter;
} __packed;

enum amd_stt_skin_temp {
	STT_TEMP_APU,
	STT_TEMP_HS2,
	STT_TEMP_COUNT,
};

enum amd_slider_op {
	SLIDER_OP_GET,
	SLIDER_OP_SET,
};

enum power_source {
	POWER_SOURCE_AC,
	POWER_SOURCE_DC,
	POWER_SOURCE_MAX,
};

enum power_modes {
	POWER_MODE_PERFORMANCE,
	POWER_MODE_BALANCED_POWER,
	POWER_MODE_POWER_SAVER,
	POWER_MODE_MAX,
};

enum power_modes_v2 {
	POWER_MODE_BEST_PERFORMANCE,
	POWER_MODE_BALANCED,
	POWER_MODE_BEST_POWER_EFFICIENCY,
	POWER_MODE_ENERGY_SAVE,
	POWER_MODE_V2_MAX,
};

struct amd_pmf_dev {
	void __iomem *regbase;
	void __iomem *smu_virt_addr;
	void *buf;
	u32 base_addr;
	u32 cpu_id;
	struct device *dev;
	struct mutex lock; /* protects the PMF interface */
	u32 supported_func;
	enum platform_profile_option current_profile;
	struct platform_profile_handler pprof;
	struct dentry *dbgfs_dir;
	int hb_interval; /* SBIOS heartbeat interval */
	struct delayed_work heart_beat;
	struct smu_pmf_metrics m_table;
	struct smu_pmf_metrics_v2 m_table_v2;
	struct delayed_work work_buffer;
	ktime_t start_time;
	int socket_power_history[AVG_SAMPLE_SIZE];
	int socket_power_history_idx;
	bool amt_enabled;
	struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
	bool cnqf_enabled;
	bool cnqf_supported;
	struct notifier_block pwr_src_notifier;
	/* Smart PC solution builder */
	struct dentry *esbin;
	unsigned char *policy_buf;
	u32 policy_sz;
	struct tee_context *tee_ctx;
	struct tee_s