// SPDX-License-Identifier: GPL-2.0
/*
* Intel Core SoC Power Management Controller Driver
*
* Copyright (c) 2016, Intel Corporation.
* All Rights Reserved.
*
* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/suspend.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/msr.h>
#include <asm/tsc.h>
#include "core.h"
/* Maximum number of modes supported by platfoms that has low power mode capability */
const char *pmc_lpm_modes[] = {
"S0i2.0",
"S0i2.1",
"S0i2.2",
"S0i3.0",
"S0i3.1",
"S0i3.2",
"S0i3.3",
"S0i3.4",
NULL
};
/* PKGC MSRs are common across Intel Core SoCs */
const struct pmc_bit_map msr_map[] = {
{"Package C2", MSR_PKG_C2_RESIDENCY},
{"Package C3", MSR_PKG_C3_RESIDENCY},
{"Package C6", MSR_PKG_C6_RESIDENCY},
{"Package C7", MSR_PKG_C7_RESIDENCY},
{"Package C8", MSR_PKG_C8_RESIDENCY},
{"Package C9", MSR_PKG_C9_RESIDENCY},
{"Package C10", MSR_PKG_C10_RESIDENCY},
{}
};
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
{
return readl(pmcdev->regbase + reg_offset);
}
static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
u32 val)
{
writel(val, pmcdev->regbase + reg_offset);
}
static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
{
/*
* ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
* used as a workaround which uses 30.5 usec tick. All other client
* programs have the legacy SLP_S0 residency counter that is using the 122
* usec tick.
*/
const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
if (pmcdev->map == &adl_reg_map)
return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
else
return (u64)value * pmcdev->map->slp_s0_res_counter_step;
}
static int set_etr3(struct pmc_dev *pmcdev)
{
const struct pmc_reg_map *map = pmcdev->map;
u32 reg;
int err;
if (!map->etr3_offset)
return -EOPNOTSUPP;
mutex_lock(&pmcdev->lock);
/* check if CF9 is locked */
reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
if (reg & ETR3_CF9LOCK) {
err = -EACCES;
goto out_unlock;
}
/* write CF9 global reset bit */
reg |= ETR3_CF9GR;
pmc_core_reg_write(pmcdev, map->etr3_offset, reg);
reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
if (!(reg & ETR3_CF9GR)) {
err = -EIO;
goto out_unlock;
}
err = 0;
out_unlock:
mutex_unlock(&pmcdev->lock);
return err;
}
static 