path: root/drivers/regulator/qcom_spmi-regulator.c

/*
 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/ktime.h>
#include <linux/regulator/driver.h>
#include <linux/regmap.h>
#include <linux/list.h>

/* Pin control enable input pins. */
#define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE		0x00
#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0		0x01
#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1		0x02
#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2		0x04
#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3		0x08
#define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT	0x10

/* Pin control high power mode input pins. */
#define SPMI_REGULATOR_PIN_CTRL_HPM_NONE		0x00
#define SPMI_REGULATOR_PIN_CTRL_HPM_EN0			0x01
#define SPMI_REGULATOR_PIN_CTRL_HPM_EN1			0x02
#define SPMI_REGULATOR_PIN_CTRL_HPM_EN2			0x04
#define SPMI_REGULATOR_PIN_CTRL_HPM_EN3			0x08
#define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B		0x10
#define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT		0x20

/*
 * Used with enable parameters to specify that hardware default register values
 * should be left unaltered.
 */
#define SPMI_REGULATOR_USE_HW_DEFAULT			2

/* Soft start strength of a voltage switch type regulator */
enum spmi_vs_soft_start_str {
	SPMI_VS_SOFT_START_STR_0P05_UA = 0,
	SPMI_VS_SOFT_START_STR_0P25_UA,
	SPMI_VS_SOFT_START_STR_0P55_UA,
	SPMI_VS_SOFT_START_STR_0P75_UA,
	SPMI_VS_SOFT_START_STR_HW_DEFAULT,
};

/**
 * struct spmi_regulator_init_data - spmi-regulator initialization data
 * @pin_ctrl_enable:        Bit mask specifying which hardware pins should be
 *				used to enable the regulator, if any
 *			    Value should be an ORing of
 *				SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants.  If
 *				the bit specified by
 *				SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
 *				set, then pin control enable hardware registers
 *				will not be modified.
 * @pin_ctrl_hpm:           Bit mask specifying which hardware pins should be
 *				used to force the regulator into high power
 *				mode, if any
 *			    Value should be an ORing of
 *				SPMI_REGULATOR_PIN_CTRL_HPM_* constants.  If
 *				the bit specified by
 *				SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
 *				set, then pin control mode hardware registers
 *				will not be modified.
 * @vs_soft_start_strength: This parameter sets the soft start strength for
 *				voltage switch type regulators.  Its value
 *				should be one of SPMI_VS_SOFT_START_STR_*.  If
 *				its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
 *				then the soft start strength will be left at its
 *				default hardware value.
 */
struct spmi_regulator_init_data {
	unsigned				pin_ctrl_enable;
	unsigned				pin_ctrl_hpm;
	enum spmi_vs_soft_start_str		vs_soft_start_strength;
};

/* These types correspond to unique register layouts. */
enum spmi_regulator_logical_type {
	SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
	SPMI_REGULATOR_LOGICAL_TYPE_LDO,
	SPMI_REGULATOR_LOGICAL_TYPE_VS,
	SPMI_REGULATOR_LOGICAL_TYPE_BOOST,
	SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS,
	SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP,
	SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO,
	SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS,
	SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
	SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO,
};

enum spmi_regulator_type {
	SPMI_REGULATOR_TYPE_BUCK		= 0x03,
	SPMI_REGULATOR_TYPE_LDO			= 0x04,
	SPMI_REGULATOR_TYPE_VS			= 0x05,
	SPMI_REGULATOR_TYPE_BOOST		= 0x1b,
	SPMI_REGULATOR_TYPE_FTS			= 0x1c,
	SPMI_REGULATOR_TYPE_BOOST_BYP		= 0x1f,
	SPMI_REGULATOR_TYPE_ULT_LDO		= 0x21,
	SPMI_REGULATOR_TYPE_ULT_BUCK		= 0x22,
};

enum spmi_regulator_subtype {
	SPMI_REGULATOR_SUBTYPE_GP_CTL		= 0x08,
	SPMI_REGULATOR_SUBTYPE_RF_CTL		= 0x09,
	SPMI_REGULATOR_SUBTYPE_N50		= 0x01,
	SPMI_REGULA