/*
* SPDX-License-Identifier: GPL-2.0
*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*
* Authors:
* Md Sadre Alam <quic_mdalam@quicinc.com>
* Sricharan R <quic_srichara@quicinc.com>
* Varadarajan Narayanan <quic_varada@quicinc.com>
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dma/qcom_adm.h>
#include <linux/dma/qcom_bam_dma.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mtd/nand-qpic-common.h>
#include <linux/mtd/spinand.h>
#include <linux/bitfield.h>
#define NAND_FLASH_SPI_CFG 0xc0
#define NAND_NUM_ADDR_CYCLES 0xc4
#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
#define NAND_FLASH_FEATURES 0xf64
/* QSPI NAND config reg bits */
#define LOAD_CLK_CNTR_INIT_EN BIT(28)
#define CLK_CNTR_INIT_VAL_VEC 0x924
#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
#define FEA_STATUS_DEV_ADDR 0xc0
#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
#define SPI_CFG BIT(0)
#define SPI_NUM_ADDR 0xDA4DB
#define SPI_WAIT_CNT 0x10
#define QPIC_QSPI_NUM_CS 1
#define SPI_TRANSFER_MODE_x1 BIT(29)
#define SPI_TRANSFER_MODE_x4 (3 << 29)
#define SPI_WP BIT(28)
#define SPI_HOLD BIT(27)
#define QPIC_SET_FEATURE BIT(31)
#define SPINAND_RESET 0xff
#define SPINAND_READID 0x9f
#define SPINAND_GET_FEATURE 0x0f
#define SPINAND_SET_FEATURE 0x1f
#define SPINAND_READ 0x13
#define SPINAND_ERASE 0xd8
#define SPINAND_WRITE_EN 0x06
#define SPINAND_PROGRAM_EXECUTE 0x10
#define SPINAND_PROGRAM_LOAD 0x84
#define ACC_FEATURE 0xe
#define BAD_BLOCK_MARKER_SIZE 0x2
#define OOB_BUF_SIZE 128
#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
struct qpic_snand_op {
u32 cmd_reg;
u32 addr1_reg;
u32 addr2_reg;
};
struct snandc_read_status {
__le32 snandc_flash;
__le32 snandc_buffer;
__le32 snandc_erased_cw;
};
/*
* ECC state struct
* @corrected: ECC corrected
* @bitfl
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