/* SPDX-License-Identifier: GPL-2.0 */
#define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 512
#ifndef XKPHYS_TO_PHYS
# define XKPHYS_TO_PHYS(p) (p)
#endif
#define OCTEON_IRQ_WORKQ0 0
#define OCTEON_IRQ_RML 0
#define OCTEON_IRQ_TIMER1 0
#define OCTEON_IS_MODEL(x) 0
#define octeon_has_feature(x) 0
#define octeon_get_clock_rate() 0
#define CVMX_SYNCIOBDMA do { } while (0)
#define CVMX_HELPER_INPUT_TAG_TYPE 0
#define CVMX_HELPER_FIRST_MBUFF_SKIP 7
#define CVMX_FAU_REG_END (2048)
#define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 16
#define CVMX_FPA_PACKET_POOL (0)
#define CVMX_FPA_PACKET_POOL_SIZE 16
#define CVMX_FPA_WQE_POOL (1)
#define CVMX_FPA_WQE_POOL_SIZE 16
#define CVMX_GMXX_RXX_ADR_CAM_EN(a, b) ((a) + (b))
#define CVMX_GMXX_RXX_ADR_CTL(a, b) ((a) + (b))
#define CVMX_GMXX_PRTX_CFG(a, b) ((a) + (b))
#define CVMX_GMXX_RXX_FRM_MAX(a, b) ((a) + (b))
#define CVMX_GMXX_RXX_JABBER(a, b) ((a) + (b))
#define CVMX_IPD_CTL_STATUS 0
#define CVMX_PIP_FRM_LEN_CHKX(a) (a)
#define CVMX_PIP_NUM_INPUT_PORTS 1
#define CVMX_SCR_SCRATCH 0
#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 2
#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 2
#define CVMX_IPD_SUB_PORT_FCS 0
#define CVMX_SSO_WQ_IQ_DIS 0
#define CVMX_SSO_WQ_INT 0
#define CVMX_POW_WQ_INT 0
#define CVMX_SSO_WQ_INT_PC 0
#define CVMX_NPI_RSL_INT_BLOCKS 0
#define CVMX_POW_WQ_INT_PC 0
union cvmx_pip_wqe_word2 {
uint64_t u64;
struct {
uint64_t bufs:8;
uint64_t ip_offset:8;
uint64_t vlan_valid:1;
uint64_t vlan_stacked:1;
uint64_t unassigned:1;
uint64_t vlan_cfi:1;
uint64_t vlan_id:12;
uint64_t pr:4;
uint64_t unassigned2:8;
uint64_t dec_ipcomp:1;
uint64_t tcp_or_udp:1;
uint64_t dec_ipsec:1;
uint64_t is_v6:1;
uint64_t software:1;
uint64_t L4_error:1;
uint64_t is_frag:1;
uint64_t IP_exc:1;
uint64_t is_bcast:1;
uint64_t is_mcast:1;
uint64_t not_IP:1;
uint64_t rcv_error:1;
uint64_t err_code:8;
} s;
struct {
uint64_t bufs:8;
uint64_t ip_offset:8;
uint64_t vlan_valid:1;
uint64_t vlan_stacked:1;
uint64_t 