// SPDX-License-Identifier: GPL-2.0
/*
* Thunderbolt driver - Tunneling support
*
* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
* Copyright (C) 2019, Intel Corporation
*/
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/list.h>
#include "tunnel.h"
#include "tb.h"
/* PCIe adapters use always HopID of 8 for both directions */
#define TB_PCI_HOPID 8
#define TB_PCI_PATH_DOWN 0
#define TB_PCI_PATH_UP 1
/* USB3 adapters use always HopID of 8 for both directions */
#define TB_USB3_HOPID 8
#define TB_USB3_PATH_DOWN 0
#define TB_USB3_PATH_UP 1
/* DP adapters use HopID 8 for AUX and 9 for Video */
#define TB_DP_AUX_TX_HOPID 8
#define TB_DP_AUX_RX_HOPID 8
#define TB_DP_VIDEO_HOPID 9
#define TB_DP_VIDEO_PATH_OUT 0
#define TB_DP_AUX_PATH_OUT 1
#define TB_DP_AUX_PATH_IN 2
static const char * const tb_tunnel_names[] = { "PCI", "DP", "DMA", "USB3" };
#define __TB_TUNNEL_PRINT(level, tunnel, fmt, arg...) \
do { \
struct tb_tunnel *__tunnel = (tunnel); \
level(__tunnel->tb, "%llx:%x <-> %llx:%x (%s): " fmt, \
tb_route(__tunnel->src_port->sw), \
__tunnel->src_port->port, \
tb_route(__tunnel->dst_port->sw), \
__tunnel->dst_port->port, \
tb_tunnel_names[__tunnel->type], \
## arg); \
} while (0)
#define tb_tunnel_WARN(tunnel, fmt, arg...) \
__TB_TUNNEL_PRINT(tb_WARN, tunnel, fmt, ##arg)
#define tb_tunnel_warn(tunnel, fmt, arg...) \
__TB_TUNNEL_PRINT(tb_warn, tunnel, fmt, ##arg)
#define tb_tunnel_info(tunnel, fmt, arg...) \
__TB_TUNNEL_PRINT(tb_info, tunnel, fmt, ##arg)
#define tb_tunnel_dbg(tunnel, fmt, arg...) \
__TB_TUNNEL_PRINT(tb_dbg, tunnel, fmt, ##arg)
static struct tb_tunnel *tb_tunnel_alloc(struct tb *tb, size_t npaths,
enum tb_tunnel_type type)
{
struct tb_tunnel *tunnel;
tunnel = kzalloc(sizeof(*tunnel), GFP_KERNEL);
if (!tunnel)
return NULL;
tunnel->paths = kcalloc(npaths, sizeof(tunnel->paths[0]), GFP_KERNEL);
if (!tunnel->paths) {
tb_tunnel_free(tunnel);
return NULL;
}
INIT_LIST_HEAD(&tunnel->list);
tunnel->tb = tb;
tunnel->npaths = npaths;
tunnel->type = type;
return tunnel;
}
static int tb_pci_activate(struct tb_tunnel *tunnel, bool activate)
{
int res;
res = tb_pci_port_enable(tunnel->src_port, activate);
if (res)
return res;
if (tb_port_is_pcie_up(tunnel->dst_port))
return tb_pci_port_enable(tunnel->dst_port, activate);
return 0;
}
static int tb_initial_credits(const struct tb_switch *sw)
{
/* If the path is complete sw is not NULL */
if (sw) {
/* More credits for faster link */
switch (sw->link_speed * sw->link_width) {
case 40:
return 32;
case 20:
return 24;
}
}
return 16;
}
static void tb_pci_init_path(struct tb_path *path)
{
path->egress_fc_enable = TB_PATH_SOURCE | TB_PATH_INTERNAL;
path->egress_shared_buffer = TB_PATH_NONE;
path->ingress_fc_enable = TB_PATH_ALL;
path->ingress_shared_buffer = TB_PATH_NONE;
path->priority = 3;
path->weight = 1;
path->drop_packages = 0;
path->nfc_credits = 0;
path->hops[0].initial_credits = 7;
if (path->path_length > 1)
path->hops[1].initial_credits =
tb_initial_credits(path->hops[1].in_port->sw);
}
/**
* tb_tunnel_discover_pci() - Discover existing PCIe tunnels
* @tb: Pointer to the domain structure
* @down: PCIe downstream adapter
*
* If @down adapter is active, follows the tunnel to the PCIe upstream
* adapter and back. Returns the discovered tunnel or %NULL if there was
* no tunnel.
*/
struct tb_tunnel *tb_tunnel_discover_pci(struct tb *tb, struct tb_port *down)
{
struct tb_tunnel *tunnel;
struct tb_path *path;
if (!tb_pci_port_is_enabled(down))
return NULL;
tunnel = tb_tunnel_alloc(tb, 2, TB_TUNNEL_PCI);
if (!tunnel)
return NULL;
tunnel->activate = tb_pci_activate;
tunnel->src_port = down;
/*
* Discover both paths even if they are not complete. We will
* clean them up by calling tb_tunnel_deactivate() below in that
* case.
*/
path = tb_path_discover(down, TB_PCI_HOPID, NULL, -1,
&tunnel->dst_port, "PCIe Up");
if (!path) {
/* Just disable the downstream port */
tb_pci_port_enable(down, false);
goto err_free;
}
tunnel->paths[TB_PCI_PATH_UP] = path;
tb_pci_init_path(tunnel->paths[TB_PCI_PATH_UP]);
path = tb_path_discover(tunnel->dst_port, -1, down, TB_PCI_HOPID, NULL,
"PCIe Down");
if (!path)
goto err_deactivate;
tunnel->paths[TB_PCI_PATH_DOWN] = path;
tb_pci_init_path(tunnel->paths[TB_PCI_PATH_DOWN]);
/* Validate that the tunnel is complete */
if (!tb_port_is_pcie_up(tunnel->dst_port)) {
tb_port_warn(tunnel->dst_port,
"path does not end on a PCIe adapter, cleaning up\n");
goto err_deactivate;
}
if (down != tunnel->src_port) {
tb_tunnel_warn(tunnel, "path is not complete, cleaning up\n");
goto err_deactivate;
}
if (!tb_pci_port_is_enabled(tunnel->dst_port)) {
tb_tunnel_warn(tunnel,
"tunnel is not fully activated, cleaning up\n");
goto err_deactivate;
}
tb_tunnel_dbg(tunnel, "discovered\n");
return tunnel;
err_deactivate:
tb_tunnel_deactivate(tunnel);
err_free:
tb_tunnel_free(tunnel);
return NULL;
}
/**
* tb_tunnel_alloc_pci() - allocate a pci tunnel
* @tb: Pointer to the domain structure
* @up: PCIe upstream adapter port
* @down: PCIe downstream adapter port
*
* Allocate a PCI tunnel. The ports must be of type TB_TYPE_PCIE_UP and
* TB_TYPE_PCIE_DOWN.
*
* Return: Returns a tb_tunnel on success or NULL on failure.
*/
struct tb_tunnel *tb_tunnel_alloc_pci(struct tb *tb, struct tb_port *up,
struct tb_port *down)
{
struct tb_tunnel *tunnel;
struct tb_path *path;
tunnel = tb_tunnel_alloc(tb, 2, TB_TUNNEL_PCI);
if (!tunnel)
return NULL;
tunnel->activate = tb_pci_activate;
tunnel->src_port = down;
tunnel->dst_port = up;
path = tb_path_alloc(tb, down, TB_PCI_HOPID, up, TB_PCI_HOPID, 0,
"PCIe Down");
if (!path) {
tb_tunnel_free(tunnel);
return NULL;
}
tb_pci_init_path(path);
tunnel->paths[TB_PCI_PATH_DOWN] = path;
path = tb_path_alloc(tb, up, TB_PCI_HOPID, down, TB_PCI_HOPID, 0,
"PCIe Up");
if (!path) {
tb_tunnel_free(tunnel);
return NULL;
}
tb_pci_init_path(path);
tunnel->paths[TB_PCI_PATH_UP] = path;
return tunnel;
}
static bool tb_dp_is_usb4(const struct tb_switch *sw)
{
/* Titan Ridge DP adapters need the same treatment as USB4 */
return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw);
}
static int tb_dp_cm_handshake(struct tb_port *in, struct tb_port *out)
{
int timeout = 10;
u32 val;
int ret;
/* Both ends need to support this */
if (!tb_dp_is_usb4(in->sw) || !tb_dp_is_usb4(out->sw))
return 0;
ret = tb_port_read(out, &val, TB_CFG_PORT,
out->cap_adap + DP_STATUS_CTRL, 1);
if (ret)
return ret;
val |= DP_STATUS_CTRL_UF | DP_STATUS_CTRL_CMHS;
ret = tb_port_write(out, &val, TB_CFG_PORT,
out->cap_adap + DP_STATUS_CTRL, 1);
if (ret)
return ret;
do {
ret = tb_port_read(out, &val, TB_CFG_PORT,
out->cap_adap + DP_STATUS_CTRL, 1);
if (ret)
return ret;
if (!(val & DP_STATUS_CTRL_CMHS))
return 0;
usleep_range(10, 100);
} while (timeout--);
return -ETIMEDOUT;
}
static inline u32 tb_dp_cap_get_rate(u32 val)
{
u32 rate = (val & DP_COMMON_CAP_RATE_MASK) >> DP_COMMON_CAP_RATE_SHIFT;
switch (rate) {
case DP_COMMON_CAP_RATE_RBR:
return 1620;
case DP_COMMON_CAP_RATE_HBR:
return 2700;
case DP_COMMON_CAP_RAT
|