path: root/drivers/usb/cdns3/cdnsp-gadget.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Cadence CDNSP DRD Driver.
 *
 * Copyright (C) 2020 Cadence.
 *
 * Author: Pawel Laszczak <pawell@cadence.com>
 *
 * Code based on Linux XHCI driver.
 * Origin: Copyright (C) 2008 Intel Corp.
 */
#ifndef __LINUX_CDNSP_GADGET_H
#define __LINUX_CDNSP_GADGET_H

#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/usb/gadget.h>
#include <linux/irq.h>

/* Max number slots - only 1 is allowed. */
#define CDNSP_DEV_MAX_SLOTS	1

#define CDNSP_EP0_SETUP_SIZE	512

/* One control and 15 for in and 15 for out endpoints. */
#define CDNSP_ENDPOINTS_NUM	31

/* Best Effort Service Latency. */
#define CDNSP_DEFAULT_BESL	0

/* Device Controller command default timeout value in us */
#define CDNSP_CMD_TIMEOUT	(15 * 1000)

/* Up to 16 ms to halt an device controller */
#define CDNSP_MAX_HALT_USEC	(16 * 1000)

#define CDNSP_CTX_SIZE	2112

/*
 * Controller register interface.
 */

/**
 * struct cdnsp_cap_regs - CDNSP Registers.
 * @hc_capbase:	Length of the capabilities register and controller
 *              version number
 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
 * @hcc_params: HCCPARAMS - Capability Parameters
 * @db_off: DBOFF - Doorbell array offset
 * @run_regs_off: RTSOFF - Runtime register space offset
 * @hcc_params2: HCCPARAMS2 Capability Parameters 2,
 */
struct cdnsp_cap_regs {
	__le32 hc_capbase;
	__le32 hcs_params1;
	__le32 hcs_params2;
	__le32 hcs_params3;
	__le32 hcc_params;
	__le32 db_off;
	__le32 run_regs_off;
	__le32 hcc_params2;
	/* Reserved up to (CAPLENGTH - 0x1C) */
};

/* hc_capbase bitmasks. */
/* bits 7:0 - how long is the Capabilities register. */
#define HC_LENGTH(p)		(((p) >> 00) & GENMASK(7, 0))
/* bits 31:16	*/
#define HC_VERSION(p)		(((p) >> 16) & GENMASK(15, 1))

/* HCSPARAMS1 - hcs_params1 - bitmasks */
/* bits 0:7, Max Device Endpoints */
#define HCS_ENDPOINTS_MASK	GENMASK(7, 0)
#define HCS_ENDPOINTS(p)	(((p) & HCS_ENDPOINTS_MASK) >> 0)

/* HCCPARAMS offset from PCI base address */
#define HCC_PARAMS_OFFSET	0x10

/* HCCPARAMS - hcc_params - bitmasks */
/* 1: device controller can use 64-bit address pointers. */
#define HCC_64BIT_ADDR(p)	((p) & BIT(0))
/* 1: device controller uses 64-byte Device Context structures. */
#define HCC_64BYTE_CONTEXT(p)	((p) & BIT(2))
/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
#define HCC_MAX_PSA(p)		((((p) >> 12) & 0xf) + 1)
/* Extended Capabilities pointer from PCI base. */
#define HCC_EXT_CAPS(p)		(((p) & GENMASK(31, 16)) >> 16)

#define CTX_SIZE(_hcc)		(HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)

/* db_off bitmask - bits 0:1 reserved. */
#define DBOFF_MASK	GENMASK(31, 2)

/* run_regs_off bitmask - bits 0:4 reserved. */
#define RTSOFF_MASK	GENMASK(31, 5)

/**
 * struct cdnsp_op_regs - Device Controller Operational Registers.
 * @command: USBCMD - Controller command register.
 * @status: USBSTS - Controller status register.
 * @page_size: This indicates the page size that the device controller supports.
 *             If bit n is set, the controller supports a page size of 2^(n+12),
 *             up to a 128MB page size. 4K is the minimum page size.
 * @dnctrl: DNCTRL - Device notification control register.
 * @cmd_ring: CRP - 64-bit Command Ring Pointer.
 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
 * @config_reg: CONFIG - Configure Register
 * @port_reg_base: PORTSCn - base address for Port Status and Control
 *                 Each port has a Port Status and Control register,
 *                 followed by a Port Power Management Status and Control
 *                 register, a Port Link Info register, and a reserved
 *                 register.
 */
struct cdnsp_op_regs {
	__le32 command;
	__le32 status;
	__le32 page_size;
	__le32 reserved1;
	__le32 reserved2;
	__le32 dnctrl;
	__le64 cmd_ring;
	/* rsvd: offset 0x20-2F. */
	__le32 reserved3[4];
	__le64 dcbaa_ptr;
	__le32 config_reg;
	/* rsvd: offset 0x3C-3FF. */
	__le32 reserved4[241];
	/* port 1 registers, which serve as a base address for other ports. */
	__le32 port_reg_base;
};

/* Number of registers per port. */
#define NUM_PORT_REGS	4

/**
 * struct cdnsp_port_regs - Port Registers.
 * @portsc: PORTSC - Port Status and Control Register.
 * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
 * @portli: PORTLI - Port Link Info register.
 */
struct cdnsp_port_regs {
	__le32 portsc;
	__le32 portpmsc;
	__le32 portli;
	__le32 reserved;
};

/*
 * These bits are Read Only (RO) and should be saved and written to the
 * reg