// SPDX-License-Identifier: GPL-2.0+
/*
* F81532/F81534 USB to Serial Ports Bridge
*
* F81532 => 2 Serial Ports
* F81534 => 4 Serial Ports
*
* Copyright (C) 2016 Feature Integration Technology Inc., (Fintek)
* Copyright (C) 2016 Tom Tsai (Tom_Tsai@fintek.com.tw)
* Copyright (C) 2016 Peter Hong (Peter_Hong@fintek.com.tw)
*
* The F81532/F81534 had 1 control endpoint for setting, 1 endpoint bulk-out
* for all serial port TX and 1 endpoint bulk-in for all serial port read in
* (Read Data/MSR/LSR).
*
* Write URB is fixed with 512bytes, per serial port used 128Bytes.
* It can be described by f81534_prepare_write_buffer()
*
* Read URB is 512Bytes max, per serial port used 128Bytes.
* It can be described by f81534_process_read_urb() and maybe received with
* 128x1,2,3,4 bytes.
*
*/
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/usb.h>
#include <linux/usb/serial.h>
#include <linux/serial_reg.h>
#include <linux/module.h>
#include <linux/uaccess.h>
/* Serial Port register Address */
#define F81534_UART_BASE_ADDRESS 0x1200
#define F81534_UART_OFFSET 0x10
#define F81534_DIVISOR_LSB_REG (0x00 + F81534_UART_BASE_ADDRESS)
#define F81534_DIVISOR_MSB_REG (0x01 + F81534_UART_BASE_ADDRESS)
#define F81534_INTERRUPT_ENABLE_REG (0x01 + F81534_UART_BASE_ADDRESS)
#define F81534_FIFO_CONTROL_REG (0x02 + F81534_UART_BASE_ADDRESS)
#define F81534_LINE_CONTROL_REG (0x03 + F81534_UART_BASE_ADDRESS)
#define F81534_MODEM_CONTROL_REG (0x04 + F81534_UART_BASE_ADDRESS)
#define F81534_LINE_STATUS_REG (0x05 + F81534_UART_BASE_ADDRESS)
#define F81534_MODEM_STATUS_REG (0x06 + F81534_UART_BASE_ADDRESS)
#define F81534_CLOCK_REG (0x08 + F81534_UART_BASE_ADDRESS)
#define F81534_CONFIG1_REG (0x09 + F81534_UART_BASE_ADDRESS)
#define F81534_DEF_CONF_ADDRESS_START 0x3000
#define F81534_DEF_CONF_SIZE 12
#define F81534_CUSTOM_ADDRESS_START 0x2f00
#define F81534_CUSTOM_DATA_SIZE 0x10
#define F81534_CUSTOM_NO_CUSTOM_DATA 0xff
#define F81534_CUSTOM_VALID_TOKEN 0xf0
#define F81534_CONF_OFFSET 1
#define F81534_CONF_INIT_GPIO_OFFSET 4
#define F81534_CONF_WORK_GPIO_OFFSET 8
#define F81534_CONF_GPIO_SHUTDOWN 7
#define F81534_CONF_GPIO_RS232 1
#define F81534_MAX_DATA_BLOCK 64
#define F81534_MAX_BUS_RETRY 20
/* Default URB timeout for USB operations */
#define F81534_USB_MAX_RETRY 10
#define F81534_USB_TIMEOUT 2000
#define F81534_SET_GET_REGISTER 0xA0
#define F81534_NUM_PORT 4
#define F81534_UNUSED_PORT 0xff
#define F81534_WRITE_BUFFER_SIZE 512
#define DRIVER_DESC "Fintek F81532/F81534"
#define FINTEK_VENDOR_ID_1 0x1934
#define FINTEK_VENDOR_ID_2 0x2C42
#define FINTEK_DEVICE_ID 0x1202
#define F81534_MAX_TX_SIZE 124
#define F81534_MAX_RX_SIZE 124
#define F81534_RECEIVE_BLOCK_SIZE 128
#define F81534_MAX_RECEIVE_BLOCK_SIZE 512
#define F81534_TOKEN_RECEIVE 0x01
#define F81534_TOKEN_WRITE 0x02
#define F81534_TOKEN_TX_EMPTY 0x03
#define F81534_TOKEN_MSR_CHANGE 0x04
/*
* We used interal SPI bus to access FLASH section. We must wait the SPI bus to
* idle if we performed any command.
*
* SPI Bus status register: F81534_BUS_REG_STATUS
* Bit 0/1 : BUSY
* Bit 2 : IDLE
*/
#define F81534_BUS_BUSY (BIT(0) | BIT(1))
#define F81534_BUS_IDLE BIT(2)
#define F81534_BUS_READ_DATA 0x1004
#define F81534_BUS_REG_STATUS 0x1003
#define F81534_BUS_REG_START 0x1002
#define F81534_BUS_REG_END 0x1001
#define F81534_CMD_READ 0x03
#define F81534_DEFAULT_BAUD_RATE 9600
#define F81534_PORT_CONF_RS232 0
#define F81534_PORT_CONF_RS485 BIT(0)
#define F81534_PORT_CONF_RS485_INVERT (BIT(0) | BIT(1))
#define F81534_PORT_CONF_MODE_MASK GENMASK(1, 0)
#define F81534_PORT_CONF_DISABLE_PORT BIT(3)
#define F81534_PORT_CONF_NOT_EXIST_PORT BIT(7)
#define F81534_PORT_UNAVAILABLE \
(F81534_PORT_CONF_DISABLE_PORT | F81534_PORT_CONF_NOT_EXIST_PORT)
#define F81534_1X_RXTRIGGER 0xc3
#define F81534_8X_RXTRIGGER 0xcf
/*
* F81532/534 Clock registers (offset +08h)
*
* Bit0: UART Enable (always on)
* Bit2-1: Clock source selector
* 00: 1.846MHz.
* 01: 18.46MHz.
* 10: 24MHz.
* 11: 14.77MHz.
* Bit4: Auto direction(RTS) control (RTS pin Low when TX)
* Bit5: Invert direction(RTS) when Bit4 enabled (RTS pin high when TX)
*/
#define F81534_UART_EN BIT(0)
#define F81534_CLK_1_846_MHZ 0
#define F81534_CLK_18_46_MHZ BIT(1)
#define F81534_CLK_24_MHZ BIT(2)
#define F81534_CLK_14_77_MHZ (BIT(1) | BIT(2))
#define F81534_CLK_MASK GENMASK(2, 1)
#define F81534_CLK_TX_DELAY_1BIT BIT(3)
#define F81534_CLK_RS485_MODE BIT(4)
#define F81534_CLK_RS485_INVERT BIT(5)
static const struct usb_device_id f81534_id_table[] = {
{ USB_DEVICE(FINTEK_VENDOR_ID_1, FINTEK_DEVICE_ID) },
{ USB_DEVICE(FINTEK_VENDOR_ID_2, FINTEK_DEVICE_ID) },
{} /* Terminating entry */
};
#define F81534_TX_EMPTY_BIT 0
struct f81534_serial_private {
u8 conf_data[F81534_DEF_CONF_SIZE];
int tty_idx[F81534_NUM_PORT];
u8 setting_idx;
int opened_port;
struct mutex urb_mutex;
};
struct f81534_port_private {
struct mutex mcr_mutex;
struct mutex lcr_mutex;
struct work_struct lsr_work;
struct usb_serial_port *port;
unsigned long tx_empty;
spinlock_t msr_lock;
u32 baud_base;
u8 shadow_mcr;
u8 shadow_lcr;
u8 shadow_msr;
u8 shadow_clk;
u8 phy_num;
};
struct f81534_pin_data {
const u16 reg_addr;
const u8 reg_mask;
};
struct f81534_port_out_pin {
struct f81534_pin_data pin[3];
};
/* Pin output value for M2/M1/M0(SD) */
static const struct f81534_port_out_pin f81534_port_out_pins[] = {
{ { { 0x2ae8, BIT(7) }, { 0x2a90, BIT(5) }, { 0x2a90, BIT(4) } } },
{ { { 0x2ae8, BIT(6) }, { 0x2ae8, BIT(0) }, { 0x2ae8, BIT(3) } } },
{ { { 0x2a90, BIT(0) }, { 0x2ae8, BIT(2) }, { 0x2a80, BIT(6) } } },
{ { { 0x2a90, BIT(3) }, { 0x2a90, BIT(2) }, { 0x2a90, BIT(1) } } },
};
static u32 const baudrate_table[] = { 115200, 921600, 1152000, 1500000 };
static u8 const clock_table[] = { F81534_CLK_1_846_MHZ, F81534_CLK_14_77_MHZ,
F81534_CLK_18_46_MHZ, F81534_CLK_24_MHZ };
static int f81534_logic_to_phy_port(struct usb_serial *serial,
struct usb_serial_port *port)
{
struct f81534_serial_private *serial_priv =
usb_get_serial_data(port->serial);
int count = 0;
int i;
for (i = 0; i < F81534_NUM_PORT; ++i) {
|