path: root/include/dt-bindings/mailbox/mediatek,mt8188-gce.h

/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
/*
 * Copyright (c) 2022 MediaTek Inc.
 *
 */
#ifndef _DT_BINDINGS_GCE_MT8188_H
#define _DT_BINDINGS_GCE_MT8188_H

#define CMDQ_THR_PRIO_LOWEST		0
#define CMDQ_THR_PRIO_1			1
#define CMDQ_THR_PRIO_2			2
#define CMDQ_THR_PRIO_3			3
#define CMDQ_THR_PRIO_4			4
#define CMDQ_THR_PRIO_5			5
#define CMDQ_THR_PRIO_6			6
#define CMDQ_THR_PRIO_HIGHEST		7

#define SUBSYS_1400XXXX                 0
#define SUBSYS_1401XXXX			1
#define SUBSYS_1402XXXX			2
#define SUBSYS_1c00XXXX			3
#define SUBSYS_1c01XXXX			4
#define SUBSYS_1c02XXXX			5
#define SUBSYS_1c10XXXX			6
#define SUBSYS_1c11XXXX			7
#define SUBSYS_1c12XXXX			8
#define SUBSYS_14f0XXXX			9
#define SUBSYS_14f1XXXX			10
#define SUBSYS_14f2XXXX			11
#define SUBSYS_1800XXXX			12
#define SUBSYS_1801XXXX			13
#define SUBSYS_1802XXXX			14
#define SUBSYS_1803XXXX			15
#define SUBSYS_1032XXXX			16
#define SUBSYS_1033XXXX			17
#define SUBSYS_1600XXXX			18
#define SUBSYS_1601XXXX			19
#define SUBSYS_14e0XXXX			20
#define SUBSYS_1c20XXXX			21
#define SUBSYS_1c30XXXX			22
#define SUBSYS_1c40XXXX			23
#define SUBSYS_1c50XXXX			24
#define SUBSYS_1c60XXXX			25
#define SUBSYS_NO_SUPPORT		99

#define CMDQ_EVENT_IMG_SOF				0
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_0		1
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_1		2
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_2		3
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_3		4
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_4		5
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_5		6
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_6		7
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_7		8
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_8		9
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_9		10
#define CMDQ_EVENT_IMG_TRAW0_DMA_ERROR_INT		11
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_0		12
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_1		13
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_2		14
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_3		15
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_4		16
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_5		17
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_6		18
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_7		19
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_8		20
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_9		21
#define CMDQ_EVENT_IMG_TRAW1_DMA_ERROR_INT		22
#define CMDQ_EVENT_IMG_ADL_RESERVED			23
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_0		24
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_1		25
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_2		26
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_3		27
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_4		28
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_5		29
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_6		30
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_7		31
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_8		32
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_9		33
#define CMDQ_EVENT_IMG_DIP_DMA_ERR			34
#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR			35
#define CMDQ_EVENT_DIP_DUMMY_0				36
#define CMDQ_EVENT_DIP_DUMMY_1				37
#define CMDQ_EVENT_DIP_DUMMY_2				38
#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE	39
#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT	40
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_0	41
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_1	42
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_2	43
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_3	44
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_4	45
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_5	46
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_6	47
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_7	48
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_8	49
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_9	50
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_0	51
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_1	52
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_2	53
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_3	54
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_4	55
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_5	56
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_6	57
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_7	58
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_8	59
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_9	60
#define CMDQ_EVENT_IMG_PQDIP_A_DMA_ERR		61
#define CMDQ_EVENT_WPE0_DUMMY_0			62
#define CMDQ_EVENT_WPE0_DUMMY_1			63
#define CMDQ_EVENT_WPE0_DUMMY_2			64
#define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE	65
#define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT	66
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_0	67
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_1	68
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_2	69
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_3	70
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_4	71
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_5	72
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_6	73
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_7	74
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_8	75
#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_9	76
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_0	77
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_1	78
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_2	79
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_3	80
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_4	81
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_5	82
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_6	83
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_7	84
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_8	85
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_9	86
#define CMDQ_EVENT_IMG_PQDIP_B_DMA_ERR		87
#define CMDQ_EVENT_WPE1_DUMMY_0			88
#define CMDQ_EVENT_WPE1_DUMMY_1			89
#define CMDQ_EVENT_WPE1_DUMMY_2			90
#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE	91
#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT	92
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_0	93
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_1	94
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_2	95
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_3	96
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_4	97
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_5	98
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_6	99
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_7	100
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_8	101
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_9	102
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_0	103
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_1	104
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_2	105
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_3	106
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_4	107
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_5	108
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_6	109
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_7	110
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_8	111
#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_9	112
#define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT	113
#define CMDQ_EVENT_WPE2_DUMMY_0			114
#define CMDQ_EVENT_WPE2_DUMMY_1			115
#define CMDQ_EVENT_WPE2_DUMMY_2			116
#define CMDQ_EVENT_IMG_IMGSYS_IPE_DUMMY		117
#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT_DONE	118
#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE	119
#define CMDQ_EVENT_IMG_IMGSYS_IPE_DVS_DONE	120
#define CMDQ_EVENT_IMG_IMGSYS_IPE_DVP_DONE	121
#define CMDQ_EVENT_FDVT1_RESERVED		122
#define CMDQ_EVENT_IMG_ENG_EVENT		123
#define CMDQ_EVENT_CAMSUBA_SW_PASS1_DONE		129
#define CMDQ_EVENT_CAMSUBB_SW_PASS1_DONE		130
#define CMDQ_EVENT_CAMSUBC_SW_PASS1_DONE		131
#define CMDQ_EVENT_GCAMSV_A_1_SW_PASS1_DONE		132
#define CMDQ_EVENT_GCAMSV_A_2_SW_PASS1_DONE		133
#define CMDQ_EVENT_GCAMSV_B_1_SW_PASS1_DONE		134
#define CMDQ_EVENT_GCAMSV_B_2_SW_PASS1_DONE		135
#define CMDQ_EVENT_GCAMSV_C_1_SW_PASS1_DONE		136
#define CMDQ_EVENT_GCAMSV_C_2_SW_PASS1_DONE		137
#define CMDQ_EVENT_GCAMSV_D_1_SW_PASS1_DONE		138
#define CMDQ_EVENT_GCAMSV_D_2_SW_PASS1_DONE		139
#define CMDQ_EVENT_GCAMSV_E_1_SW_PASS1_DONE		140
#define CMDQ_EVENT_GCAMSV_E_2_SW_PASS1_DONE		141
#define CMDQ_EVENT_GCAMSV_F_1_SW_PASS1_DONE		142
#define CMDQ_EVENT_GCAMSV_F_2_SW_PASS1_DONE		143
#define CMDQ_EVENT_GCAMSV_G_1_SW_PASS1_DONE		144
#define CMDQ_EVENT_GCAMSV_G_2_SW_PASS1_DONE		145
#define CMDQ_EVENT_GCAMSV_H_1_SW_PASS1_DONE		146
#define CMDQ_EVENT_GCAMSV_H_2_SW_PASS1_DONE		147
#define CMDQ_EVENT_GCAMSV_I_1_SW_PASS1_DONE		148
#define CMDQ_EVENT_GCAMSV_I_2_SW_PASS1_DONE		149
#define CMDQ_EVENT_GCAMSV_J_1_SW_PASS1_DONE		150
#define CMDQ_EVENT_GCAMSV_J_2_SW_PASS1_DONE		151
#define CMDQ_EVENT_MRAW_0_SW_PASS1_DONE			152
#define CMDQ_EVENT_MRAW_1_SW_PASS1_DONE			153
#define CMDQ_EVENT_MRAW_2_SW_PASS1_DONE			154
#define CMDQ_EVENT_MRAW_3_SW_PASS1_DONE			155
#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL		156
#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL		157
#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL		158
#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL		159
#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL		160
#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL		161
#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL		162
#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL		163
#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL		164
#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL		165
#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL		166
#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL		167
#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL		168
#define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL		169
#define CMDQ_EVENT_SENINF_CAM14_FIFO_FULL		170
#define CMDQ_EVENT_SENINF_CAM15_FIFO_FULL		171
#define CMDQ_EVENT_SENINF_CAM16_FIFO_FULL		172
#define CMDQ_EVENT_SENINF_CAM17_FIFO_FULL		173
#define CMDQ_EVENT_SENINF_CAM18_FIFO_FULL		174
#define CMDQ_EVENT_SENINF_CAM19_FIFO_FULL		175
#define CMDQ_EVENT_SENINF_CAM20_FIFO_FULL		176
#define CMDQ_EVENT_SENINF_CAM21_FIFO_FULL		177
#define CMDQ_EVENT_SENINF_CAM22_FIFO_FULL		178
#define CMDQ_EVENT_SENINF_CAM23_FIFO_FULL		179
#define CMDQ_EVENT_SENINF_CAM24_FIFO_FULL		180
#define CMDQ_EVENT_SENINF_CAM25_FIFO_FULL		181
#define CMDQ_EVENT_SENINF_CAM26_FIFO_FULL		182
#define CMDQ_EVENT_TG_OVRUN_MRAW0_INT			183
#define CMDQ_EVENT_TG_OVRUN_MRAW1_INT			184
#define CMDQ_EVENT_TG_OVRUN_MRAW2_INT			185
#define CMDQ_EVENT_TG_OVRUN_MRAW3_INT			186
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT		187
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT		188
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT		189
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT		190
#define CMDQ_EVENT_PDA0_IRQO_EVENT_DONE_D1		191
#define CMDQ_EVENT_PDA1_IRQO_EVENT_DONE_D1		192
#define CMDQ_EVENT_CAM_SUBA_TG_INT1				193
#define CMDQ_EVENT_CAM_SUBA_TG_INT2				194
#define CMDQ_EVENT_CAM_SUBA_TG_INT3				195
#define CMDQ_EVENT_CAM_SUBA_TG_INT4				196
#define CMDQ_EVENT_CAM_SUBB_TG_INT1				197
#define CMDQ_EVENT_CAM_SUBB_TG_INT2				198
#define CMDQ_EVENT_CAM_SUBB_TG_INT3				199
#define CMDQ_EVENT_CAM_SUBB_TG_INT4				200
#define CMDQ_EVENT_CAM_SUBC_TG_INT1				201
#define CMDQ_EVENT_CAM_SUBC_TG_INT2				202
#define CMDQ_EVENT_CAM_SUBC_TG_INT3				203
#define CMDQ_EVENT_CAM_SUBC_TG_INT4				204
#define CMDQ_EVENT_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	205
#define CMDQ_EVENT_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	206
#define CMDQ_EVENT_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	207
#define CMDQ_EVENT_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	208
#define CMDQ_EVENT_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	209
#define CMDQ_EVENT_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	210
#define CMDQ_EVENT_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	211
#define CMDQ_EVENT_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	212
#define CMDQ_EVENT_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	213
#define CMDQ_EVENT_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	214
#define CMDQ_EVENT_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	215
#define CMDQ_EVENT_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	216
#define CMDQ_EVENT_RAW_SEL_SOF_SUBA				217
#define CMDQ_EVENT_RAW_SEL_SOF_SUBB				218
#define CMDQ_EVENT_RAW_SEL_SOF_SUBC				219
#define CMDQ_EVENT_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN		220
#define CMDQ_EVENT_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN		221
#define CMDQ_EVENT_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN		222
#define CMDQ_EVENT_VPP0_MDP_RDMA_SOF				256
#define CMDQ_EVENT_VPP0_MDP_FG_SOF				257
#define CMDQ_EVENT_VPP0_STITCH_SOF				258
#define CMDQ_EVENT_VPP0_MDP_HDR_SOF				259
#define CMDQ_EVENT_VPP0_MDP_AAL_SOF				260
#define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF			261
#define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF				262
#define CMDQ_EVENT_VPP0_DISP_COLOR_SOF				263
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF			264
#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF		265
#define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF				266
#define CMDQ_EVENT_VPP0_MDP_WROT_SOF				267
#define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE		269
#define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE		270
#define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF		271
#define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE		272
#define CMDQ_EVENT_VPP0_DISP_RDMA_SOF				273
#define CMDQ_EVENT_VPP0_DISP_WDMA_SOF				274
#define CMDQ_EVENT_VPP0_MDP_HMS_SOF				275
#define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE			288
#define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE			289
#define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE			290
#define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE			291
#define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE			292
#define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE			293
#define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE			294
#define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE			295
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE		296
#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE	297
#define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE			298
#define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE			299
#define CMDQ_EVENT_VPP0_DISP_RDMA_FRAME_DONE			305
#define CMDQ_EVENT_VPP0_DISP_WDMA_FRAME_DONE			306
#define CMDQ_EVENT_VPP0_MDP_HMS_FRAME_DONE			307
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_0		320
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_1		321
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_2		322
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_3		323
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_4		324
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_5		325
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_6		326
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_7		327
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_8		328
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_9		329
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_10		330
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_11		331
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_12		332
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_13		333
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_14		334
#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_15		335
#define CMDQ_EVENT_VPP0_DISP_RDMA_0_UNDERRUN			336
#define CMDQ_EVENT_VPP0_DISP_RDMA_1_UNDERRUN			337
#define CMDQ_EVENT_VPP0_U_MERGE4_UNDERRUN			338
#define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_0_OVERFLOW		339
#define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_1_OVERFLOW		340
#define CMDQ_EVENT_VPP0_DSI_0_UNDERRUN				341
#define CMDQ_EVENT_VPP0_DSI_1_UNDERRUN				342
#define CMDQ_EVENT_VPP0_DP_INTF_0				343
#define CMDQ_EVENT_VPP0_DP_INTF_1				344
#define CMDQ_EVENT_VPP0_DPI_0					345
#define CMDQ_EVENT_VPP0_DPI_1					346
#define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE			352
#define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID_EVENT			353
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE	354
#define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE			355
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_0		356
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_1		357
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_2		358
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_3		359
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_4		360
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_5		361
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_6		362
#define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_VALID_EVENT		363
#define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_TARGET_LINE_EVENT	364
#define CMDQ_EVENT_VPP0_DISP_WDMA_SW_RST_DONE			365
#define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_VALID_EVENT		366
#define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_TARGET_LINE_EVENT	367
#define CMDQ_EVENT_VPP1_HDMI_META_SOF				384
#define CMD