path: root/include/linux/mfd/tps6594.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Functions to access TPS6594 Power Management IC
 *
 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
 */

#ifndef __LINUX_MFD_TPS6594_H
#define __LINUX_MFD_TPS6594_H

#include <linux/device.h>
#include <linux/regmap.h>

struct regmap_irq_chip_data;

/* Chip id list */
enum pmic_id {
	TPS6594,
	TPS6593,
	LP8764,
	TPS65224,
};

/* Macro to get page index from register address */
#define TPS6594_REG_TO_PAGE(reg)	((reg) >> 8)

/* Registers for page 0 */
#define TPS6594_REG_DEV_REV				0x01

#define TPS6594_REG_NVM_CODE_1				0x02
#define TPS6594_REG_NVM_CODE_2				0x03

#define TPS6594_REG_BUCKX_CTRL(buck_inst)		(0x04 + ((buck_inst) << 1))
#define TPS6594_REG_BUCKX_CONF(buck_inst)		(0x05 + ((buck_inst) << 1))
#define TPS6594_REG_BUCKX_VOUT_1(buck_inst)		(0x0e + ((buck_inst) << 1))
#define TPS6594_REG_BUCKX_VOUT_2(buck_inst)		(0x0f + ((buck_inst) << 1))
#define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst)		(0x18 + (buck_inst))

#define TPS6594_REG_LDOX_CTRL(ldo_inst)			(0x1d + (ldo_inst))
#define TPS6594_REG_LDORTC_CTRL				0x22
#define TPS6594_REG_LDOX_VOUT(ldo_inst)			(0x23 + (ldo_inst))
#define TPS6594_REG_LDOX_PG_WINDOW(ldo_inst)		(0x27 + (ldo_inst))

#define TPS6594_REG_VCCA_VMON_CTRL			0x2b
#define TPS6594_REG_VCCA_PG_WINDOW			0x2c
#define TPS6594_REG_VMON1_PG_WINDOW			0x2d
#define TPS6594_REG_VMON1_PG_LEVEL			0x2e
#define TPS6594_REG_VMON2_PG_WINDOW			0x2f
#define TPS6594_REG_VMON2_PG_LEVEL			0x30

#define TPS6594_REG_GPIOX_CONF(gpio_inst)		(0x31 + (gpio_inst))
#define TPS6594_REG_NPWRON_CONF				0x3c
#define TPS6594_REG_GPIO_OUT_1				0x3d
#define TPS6594_REG_GPIO_OUT_2				0x3e
#define TPS6594_REG_GPIO_IN_1				0x3f
#define TPS6594_REG_GPIO_IN_2				0x40
#define TPS6594_REG_GPIOX_OUT(gpio_inst)		(TPS6594_REG_GPIO_OUT_1 + (gpio_inst) / 8)
#define TPS6594_REG_GPIOX_IN(gpio_inst)			(TPS6594_REG_GPIO_IN_1 + (gpio_inst) / 8)

#define TPS6594_REG_RAIL_SEL_1				0x41
#define TPS6594_REG_RAIL_SEL_2				0x42
#define TPS6594_REG_RAIL_SEL_3				0x43

#define TPS6594_REG_FSM_TRIG_SEL_1			0x44
#define TPS6594_REG_FSM_TRIG_SEL_2			0x45
#define TPS6594_REG_FSM_TRIG_MASK_1			0x46
#define TPS6594_REG_FSM_TRIG_MASK_2			0x47
#define TPS6594_REG_FSM_TRIG_MASK_3			0x48

#define TPS6594_REG_MASK_BUCK1_2			0x49
#define TPS65224_REG_MASK_BUCKS				0x49
#define TPS6594_REG_MASK_BUCK3_4			0x4a
#define TPS6594_REG_MASK_BUCK5				0x4b
#define TPS6594_REG_MASK_LDO1_2				0x4c
#define TPS65224_REG_MASK_LDOS				0x4c
#define TPS6594_REG_MASK_LDO3_4				0x4d
#define TPS6594_REG_MASK_VMON				0x4e
#define TPS6594_REG_MASK_GPIO_FALL			0x4f
#define TPS6594_REG_MASK_GPIO_RISE			0x50
#define TPS6594_REG_MASK_GPIO9_11			0x51
#define TPS6594_REG_MASK_STARTUP			0x52
#define TPS6594_REG_MASK_MISC				0x53
#define TPS6594_REG_MASK_MODERATE_ERR			0x54
#define TPS6594_REG_MASK_FSM_ERR			0x56
#define TPS6594_REG_MASK_COMM_ERR			0x57
#define TPS6594_REG_MASK_READBACK_ERR			0x58
#define TPS6594_REG_MASK_ESM				0x59

#define TPS6594_REG_INT_TOP				0x5a
#define TPS6594_REG_INT_BUCK				0x5b
#define TPS6594_REG_INT_BUCK1_2				0x5c
#define TPS6594_REG_INT_BUCK3_4				0x5d
#define TPS6594_REG_INT_BUCK5				0x5e
#define TPS6594_REG_INT_LDO_VMON			0x5f
#define TPS6594_REG_INT_LDO1_2				0x60
#define TPS6594_REG_INT_LDO3_4				0x61
#define TPS6594_REG_INT_VMON				0x62
#define TPS6594_REG_INT_GPIO				0x63
#define TPS6594_REG_INT_GPIO1_8				0x64
#define TPS6594_REG_INT_STARTUP				0x65
#define TPS6594_REG_INT_MISC				0x66
#define TPS6594_REG_INT_MODERATE_ERR			0x67
#define TPS6594_REG_INT_SEVERE_ERR			0x68
#define TPS6594_REG_INT_FSM_ERR				0x69
#define TPS6594_REG_INT_COMM_ERR			0x6a
#define TPS6594_REG_INT_READBACK_ERR			0x6b
#define TPS6594_REG_INT_ESM				0x6c

#define TPS6594_REG_STAT_BUCK1_2			0x6d
#define TPS6594_REG_STAT_BUCK3_4			0x6e
#define TPS6594_REG_STAT_BUCK5				0x6f
#define TPS6594_REG_STAT_LDO1_2				0x70
#define TPS6594_REG_STAT_LDO3_4				0x71
#define TPS6594_REG_STAT_VMON				0x72
#define TPS6594_REG_STAT_STARTUP			0x73
#define TPS6594_REG_STAT_MISC				0x74
#define TPS6594_REG_STAT_MODERATE_ERR			0x75
#define TPS6594_REG_STAT_SEVERE_ERR			0x76
#define TPS6594_REG_STAT_READBACK_ERR			0x77

#define TPS6594_REG_PGOOD_SEL_1				0x78
#define TPS6594_REG_PGOOD_SEL_2				0x79
#define TPS6594_REG_PGOOD_SEL_3				0x7a
#define TPS6594_REG_PGOOD_SEL_4				0x7b

#define TPS6594_REG_PLL_CTRL				0x7c

#define TPS6594_REG_CONFIG_1				0x7d
#define TPS6594_REG_CONFIG_2				0x7e

#define TPS6594_REG_ENABLE_DRV_REG			0x80

#define TPS6594_REG_MISC_CTRL				0x81

#define TPS6594_REG_ENABLE_DRV_STAT			0x82

#define TPS6594_REG_RECOV_CNT_REG_1			0x83
#define TPS6594_REG_RECOV_CNT_REG_2			0x84

#define TPS6594_REG_FSM_I2C_TRIGGERS			0x85
#define TPS6594_REG_FSM_NSLEEP_TRIGGERS			0x86

#define TPS6594_REG_BUCK_RESET_REG			0x87

#define TPS6594_REG_SPREAD_SPECTRUM_1			0x88

#define TPS6594_REG_FREQ_SEL				0x8a

#define TPS6594_REG_FSM_STEP_SIZE			0x8b

#define TPS6594_REG_LDO_RV_TIMEOUT_REG_1		0x8c
#define TPS6594_REG_LDO_RV_TIMEOUT_REG_2		0x8d

#define TPS6594_REG_USER_SPARE_REGS			0x8e

#define TPS6594_REG_ESM_MCU_START_REG			0x8f
#define TPS6594_REG_ESM_MCU_DELAY1_REG			0x90
#define TPS6594_REG_ESM_MCU_DELAY2_REG			0x91
#define TPS6594_REG_ESM_MCU_MODE_CFG			0x92
#define TPS6594_REG_ESM_MCU_HMAX_REG			0x93
#define TPS6594_REG_ESM_MCU_HMIN_REG			0x94
#define TPS6594_REG_ESM_MCU_LMAX_REG			0x95
#define TPS6594_REG_ESM_MCU_LMIN_REG			0x96
#define TPS6594_REG_ESM_MCU_ERR_CNT_REG			0x97
#define TPS6594_REG_ESM_SOC_START_REG			0x98
#define TPS6594_REG_ESM_SOC_DELAY1_REG			0x99
#define TPS6594_REG_ESM_SOC_DELAY2_REG			0x9a
#define TPS6594_REG_ESM_SOC_MODE_CFG			0x9b
#define TPS6594_REG_ESM_SOC_HMAX_REG			0x9c
#define TPS6594_REG_ESM_SOC_HMIN_REG			0x9d
#define TPS6594_REG_ESM_SOC_LMAX_REG			0x9e
#define TPS6594_REG_ESM_SOC_LMIN_REG			0x9f
#define TPS6594_REG_ESM_SOC_ERR_CNT_REG			0xa0

#define TPS6594_REG_REGISTER_LOCK			0xa1

#define TPS65224_REG_SRAM_ACCESS_1			0xa2
#define TPS65224_REG_SRAM_ACCESS_2			0xa3
#define TPS65224_REG_SRAM_ADDR_CTRL			0xa4
#define TPS65224_REG_RECOV_CNT_PFSM_INCR		0xa5
#define TPS6594_REG_MANUFACTURING_VER			0xa6

#define TPS6594_REG_CUSTOMER_NVM_ID_REG			0xa7

#define TPS6594_REG_VMON_CONF_REG			0xa8

#define TPS6594_REG_SOFT_REBOOT_REG			0xab

#define TPS65224_REG_ADC_CTRL				0xac
#define TPS65224_REG_ADC_RESULT_REG_1			0xad
#define TPS65224_REG_ADC_RESULT_REG_2			0xae
#define TPS6594_REG_RTC_SECONDS				0xb5
#define TPS6594_REG_RTC_MINUTES				0xb6
#define TPS6594_REG_RTC_HOURS				0xb7
#define TPS6594_REG_RTC_DAYS				0xb8
#define TPS6594_REG_RTC_MONTHS				0xb9
#define TPS6594_REG_RTC_YEARS				0xba
#define TPS6594_REG_RTC_WEEKS				0xbb

#define TPS6594_REG_ALARM_SECONDS			0xbc
#define TPS6594_REG_ALARM_MINUTES			0xbd
#define TPS6594_REG_ALARM_HOURS				0xbe
#define TPS6594_REG_ALARM_DAYS				0xbf
#define TPS6594_REG_ALARM_MONTHS			0xc0
#define TPS6594_REG_ALARM_YEARS				0xc1

#define TPS6594_REG_RTC_CTRL_1				0xc2
#define TPS6594_REG_RTC_CTRL_2				0xc3
#define TPS65224_REG_STARTUP_CTRL			0xc3
#define TPS6594_REG_RTC_STATUS				0xc4
#define TPS6594_REG_RTC_INTERRUPTS			0xc5
#define TPS6594_REG_RTC_COMP_LSB			0xc6
#define TPS6594_REG_RTC_COMP_MSB			0xc7
#define TPS6594_REG_RTC_RESET_STATUS			0xc8

#define TPS6594_REG_SCRATCH_PAD_REG_1			0xc9
#define TPS6594_REG_SCRATCH_PAD_REG_2			0xca
#define TPS6594_REG_SCRATCH_PAD_REG_3			0xcb
#define TPS6594_REG_SCRATCH_PAD_REG_4			0xcc

#define TPS6594_REG_PFSM_DELAY_REG_1			0xcd
#define TPS6594_REG_PFSM_DELAY_REG_2			0xce
#define TPS6594_REG_PFSM_DELAY_REG_3			0xcf
#define TPS6594_REG_PFSM_DELAY_REG_4			0xd0
#define TPS65224_REG_ADC_GAIN_COMP_REG			0xd0
#define TPS65224_REG_CRC_CALC_CONTROL			0xef
#define TPS65224_REG_REGMAP_USER_CRC_LOW		0xf0
#define TPS65224_REG_REGMAP_USER_CRC_HIGH		0xf1

/* Registers for page 1 */
#define TPS6594_REG_SERIAL_IF_CONFIG			0x11a
#define TPS6594_REG_I2C1_ID				0x122
#define TPS6594_REG_I2C2_ID				0x123

/* Registers for page 4 */
#define TPS6594_REG_WD_ANSWER_REG			0x401
#define TPS6594_REG_WD_QUESTION_ANSW_CNT		0x402
#define TPS6594_REG_WD_WIN1_CFG				0x403
#define TPS6594_REG_WD_WIN2_CFG				0x404
#define TPS6594_REG_WD_LONGWIN_CFG			0x405
#define TPS6594_REG_WD_MODE_REG				0x406
#define TPS6594_REG_WD_QA_CFG				0x407
#define TPS6594_REG_WD_ERR_STATUS			0x408
#define TPS6594_REG_WD_THR_CFG				0x409
#define TPS6594_REG_DWD_FAIL_CNT_REG			0x40a

/* BUCKX_CTRL register field definition */
#define TPS6594_BIT_BUCK_EN				BIT(0)
#define TPS6594_BIT_BUCK_FPWM				BIT(1)
#define TPS6594_BIT_BUCK_FPWM_MP			BIT(2)
#define TPS6594_BIT_BUCK_VSEL				BIT(3)
#define TPS6594_BIT_BUCK_VMON_EN			BIT(4)
#define TPS6594_BIT_BUCK_PLDN				BIT(5)
#define TPS6594_BIT_BUCK_RV_SEL				BIT(7)

/* TPS6594 BUCKX_CONF register field definition */
#define TPS6594_MASK_BUCK_SLEW_RATE			GENMASK(2, 0)
#define TPS6594_MASK_BUCK_ILIM				GENMASK(5, 3)

/* TPS65224 BUCKX_CONF register field definition */
#define TPS65224_MASK_BUCK_SLEW_RATE			GENMASK(1, 0)

/* TPS6594 BUCKX_PG_WINDOW register field definition */
#define TPS6594_MASK_BUCK_OV_THR			GENMASK(2, 0)
#define TPS6594_MASK_BUCK_UV_THR			GENMASK(5, 3)

/* TPS65224 BUCKX_PG_WINDOW register field definition */
#define TPS65224_MASK_BUCK_VMON_THR			GENMASK(1, 0)

/* TPS6594 BUCKX_VOUT register field definition */
#define TPS6594_MASK_BUCKS_VSET				GENMASK(7, 0)

/* TPS65224 BUCKX_VOUT register field definition */
#define TPS65224_MASK_BUCK1_VSET			GENMASK(7, 0)
#define TPS65224_MASK_BUCKS_VSET			GENMASK(6, 0)

/* LDOX_CTRL register field definition */
#define TPS6594_BIT_LDO_EN				BIT(0)
#define TPS6594_BIT_LDO_SLOW_RAMP			BIT(1)
#define TPS6594_BIT_LDO_VMON_EN				BIT(4)
#define TPS6594_MASK_LDO_PLDN				GENMASK(6, 5)
#define TPS6594_BIT_LDO_RV_SEL				BIT(7)
#define TPS65224_BIT_LDO_DISCHARGE_EN			BIT(5)

/* LDORTC_CTRL register field definition */
#define TPS6594_BIT_LDORTC_DIS				BIT(0)

/* LDOX_VOUT register field definition */
#define TPS6594_MASK_LDO123_VSET			GENMASK(6, 1)
#define TPS6594_MASK_LDO4_VSET				GENMASK(6, 0)
#define TPS6594_BIT_LDO_BYPASS				BIT(7)

/* LDOX_PG_WINDOW register field definition */
#define TPS6594_MASK_LDO_OV_THR				GENMASK(2, 0)
#define TPS6594_MASK_LDO_UV_THR				GENMASK(5, 3)

/* LDOX_PG_WINDOW register field definition */
#define TPS65224_MASK_LDO_VMON_THR			GENMASK(1, 0)

/* VCCA_VMON_CTRL register field definition */
#define TPS6594_BIT_VMON_EN				BIT(0)
#define TPS6594_BIT_VMON1_EN				BIT(1)
#define TPS6594_BIT_VMON1_RV_SEL			BIT(2)
#define TPS6594_BIT_VMON2_EN				BIT(3)
#define TPS6594_BIT_VMON2_RV_SEL			BIT(4)
#define TPS6594_BIT_VMON_DEGLITCH_SEL			BIT(5)
#define TPS65224_BIT_VMON_DEGLITCH_SEL			GENMASK(7, 5)

/* VCCA_PG_WINDOW register field definition */
#define TPS6594_MASK_VCCA_OV_THR			GENMASK(2, 0)
#define TPS6594_MASK_VCCA_UV_THR			GENMASK(5, 3)
#define TPS65224_MASK_VCCA_VMON_THR			GENMASK(1, 0)
#define TPS6594_BIT_VCCA_PG_SET				BIT(6)

/* VMONX_PG_WINDOW register field definition */
#define TPS6594_MASK_VMONX_OV_THR			GENMASK(2, 0)
#define TPS6594_MASK_VMONX_UV_THR			GENMASK(5, 3)
#define TPS6594_BIT_VMONX_RANGE				BIT(6)

/* VMONX_PG_WINDOW register field definition */
#define TPS65224_MASK_VMONX_THR				GENMASK(1, 0)

/* GPIOX_CONF register field definition */
#define TPS6594_BIT_GPIO_DIR				BIT(0)
#define TPS6594_BIT_GPIO_OD				BIT(1)
#define TPS6594_BIT_GPIO_PU_SEL				BIT(2)
#define TPS6594_BIT_GPIO_PU_PD_EN			BIT(3)
#define TPS6594_BIT_GPIO_DEGLITCH_EN			BIT(4)
#define TPS6594_MASK_GPIO_SEL				GENMASK(7, 5)
#define TPS65224_MASK_GPIO_SEL				GENMASK(6, 5)
#define TPS65224_MASK_GPIO_SEL_GPIO6			GENMASK(7, 5)

/* NPWRON_CONF register field definition */
#define TPS6594_BIT_NRSTOUT_OD				BIT(0)
#define TPS6594_BIT_ENABLE_PU_SEL			BIT(2)
#define TPS6594_BIT_ENABLE_PU_PD_EN			BIT(3)
#define TPS6594_BIT_ENABLE_DEGLITCH_EN			BIT(4)
#define TPS6594_BIT_ENABLE_POL				BIT(5)
#define TPS6594_MASK_NPWRON_SEL				GENMASK(7, 6)

/* POWER_ON_CONFIG register field definition */
#define TPS65224_BIT_NINT_ENDRV_PU_SEL			BIT(0)
#define TPS65224_BIT_NINT_ENDRV_SEL			BIT(1)
#define TPS65224_BIT_EN_PB_DEGL				BIT(5)
#define TPS65224_MASK_EN_PB_VSENSE_CONFIG		GENMASK(7, 6)

/* GPIO_OUT_X register field definition */
#define TPS6594_BIT_GPIOX_OUT(gpio_inst)		BIT((gpio_inst) % 8)

/* GPIO_IN_X register field definition */
#define TPS6594_BIT_GPIOX_IN(gpio_inst)			BIT((gpio_inst) % 8)
#define TPS6594_BIT_NPWRON_IN				BIT(3)

/* GPIO_OUT_X register field definition */
#define TPS65224_BIT_GPIOX_OUT(gpio_inst)		BIT((gpio_inst))

/* GPIO_IN_X register field definition */
#define TPS65224_BIT_GPIOX_IN(gpio_inst)		BIT((gpio_inst))

/* RAIL_SEL_1 register field definition */
#define TPS6594_MASK_BUCK1_GRP_SEL			GENMASK(1, 0)
#define TPS6594_MASK_BUCK2_GRP_SEL			GENMASK(3, 2)
#define TPS6594_MASK_BUCK3_GRP_SEL			GENMASK(5, 4)
#define TPS6594_MASK_BUCK4_GRP_SEL			GENMASK(7, 6)

/* RAIL_SEL_2 register field definition */
#define TPS6594_MASK_BUCK5_GRP_SEL			GENMASK(1, 0)
#define TPS6594_MASK_LDO1_GRP_SEL			GENMASK(3, 2)
#define TPS6594_MASK_LDO2_GRP_SEL			GENMASK(5, 4)
#define TPS6594_MASK_LDO3_GRP_SEL			GENMASK(7, 6)

/* RAIL_SEL_3 register field definition */
#define TPS6594_MASK_LDO4_GRP_SEL			GENMASK(1, 0)
#define TPS6594_MASK_VCCA_GRP_SEL			GENMASK(3, 2)
#define TPS6594_MASK_VMON1_GRP_SEL			GENMASK(5, 4)
#define TPS6594_MASK_VMON2_GRP_SEL			GENMASK(7, 6)

/* FSM_TRIG_SEL_1 register field definition */
#define TPS6594_MASK_MCU_RAIL_TRIG			GENMASK(1, 0)
#define TPS6594_MASK_SOC_RAIL_TRIG			GENMASK(3, 2)
#define TPS6594_MASK_OTHER_RAIL_TRIG			GENMASK(5, 4)
#define TPS6594_MASK_SEVERE_ERR_TRIG			GENMASK(7, 6)

/* FSM_TRIG_SEL_2 register field definition */
#define TPS6594_MASK_MODERATE_ERR_TRIG			GENMASK(1, 0)

/* FSM_TRIG_MASK_X register field definition */
#define TPS6594_BIT_GPIOX_FSM_MASK(gpio_inst)		BIT(((gpio_inst) << 1) % 8)
#define TPS6594_BIT_GPIOX_FSM_MASK_POL(gpio_inst)	BIT(((gpio_inst) << 1) % 8 + 1)

#define TPS65224_BIT_GPIOX_FSM_MASK(gpio_inst)		BIT(((gpio_inst) << 1) % 6)
#define TPS65224_BIT_GPIOX_FSM_MASK_POL(gpio_inst)	BIT(((gpio_inst) << 1) % 6 + 1)

/* MASK_BUCKX register field definition */
#define TPS6594_BIT_BUCKX_OV_MASK(buck_inst)		BIT(((buck_inst) << 2) % 8)
#define TPS6594_BIT_BUCKX_UV_MASK(buck_inst)		BIT(((buck_inst) << 2) % 8 + 1)
#define TPS6594_BIT_BUCKX_ILIM_MASK(buck_inst)		BIT(((buck_inst) << 2) % 8 + 3)

/* MASK_LDOX register field definition */
#define TPS6594_BIT_LDOX_OV_MASK(ldo_inst)		BIT(((ldo_inst) << 2) % 8)
#define TPS6594_BIT_LDOX_UV_MASK(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 1)
#define TPS6594_BIT_LDOX_ILIM_MASK(ldo_inst)		BIT(((ldo_inst) << 2) % 8 + 3)

/* MASK_VMON register field definition */
#define TPS6594_BIT_VCCA_OV_MASK			BIT(0)
#define TPS6594_BIT_