path: root/include/sound/cs35l41.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * linux/sound/cs35l41.h -- Platform data for CS35L41
 *
 * Copyright (c) 2017-2021 Cirrus Logic Inc.
 *
 * Author: David Rhodes	<david.rhodes@cirrus.com>
 */

#ifndef __CS35L41_H
#define __CS35L41_H

#include <linux/regmap.h>
#include <linux/firmware/cirrus/cs_dsp.h>

#define CS35L41_FIRSTREG		0x00000000
#define CS35L41_LASTREG			0x03804FE8
#define CS35L41_DEVID			0x00000000
#define CS35L41_REVID			0x00000004
#define CS35L41_FABID			0x00000008
#define CS35L41_RELID			0x0000000C
#define CS35L41_OTPID			0x00000010
#define CS35L41_SFT_RESET		0x00000020
#define CS35L41_TEST_KEY_CTL		0x00000040
#define CS35L41_USER_KEY_CTL		0x00000044
#define CS35L41_OTP_MEM0		0x00000400
#define CS35L41_OTP_MEM31		0x0000047C
#define CS35L41_OTP_CTRL0		0x00000500
#define CS35L41_OTP_CTRL1		0x00000504
#define CS35L41_OTP_CTRL3		0x00000508
#define CS35L41_OTP_CTRL4		0x0000050C
#define CS35L41_OTP_CTRL5		0x00000510
#define CS35L41_OTP_CTRL6		0x00000514
#define CS35L41_OTP_CTRL7		0x00000518
#define CS35L41_OTP_CTRL8		0x0000051C
#define CS35L41_PWR_CTRL1		0x00002014
#define CS35L41_PWR_CTRL2		0x00002018
#define CS35L41_PWR_CTRL3		0x0000201C
#define CS35L41_CTRL_OVRRIDE		0x00002020
#define CS35L41_AMP_OUT_MUTE		0x00002024
#define CS35L41_PROTECT_REL_ERR_IGN	0x00002034
#define CS35L41_GPIO_PAD_CONTROL	0x0000242C
#define CS35L41_JTAG_CONTROL		0x00002438
#define CS35L41_PWRMGT_CTL		0x00002900
#define CS35L41_WAKESRC_CTL		0x00002904
#define CS35L41_PWRMGT_STS		0x00002908
#define CS35L41_PLL_CLK_CTRL		0x00002C04
#define CS35L41_DSP_CLK_CTRL		0x00002C08
#define CS35L41_GLOBAL_CLK_CTRL		0x00002C0C
#define CS35L41_DATA_FS_SEL		0x00002C10
#define CS35L41_TST_FS_MON0		0x00002D10
#define CS35L41_MDSYNC_EN		0x00003400
#define CS35L41_MDSYNC_TX_ID		0x00003408
#define CS35L41_MDSYNC_PWR_CTRL		0x0000340C
#define CS35L41_MDSYNC_DATA_TX		0x00003410
#define CS35L41_MDSYNC_TX_STATUS	0x00003414
#define CS35L41_MDSYNC_DATA_RX		0x0000341C
#define CS35L41_MDSYNC_RX_STATUS	0x00003420
#define CS35L41_MDSYNC_ERR_STATUS	0x00003424
#define CS35L41_MDSYNC_SYNC_PTE2	0x00003528
#define CS35L41_MDSYNC_SYNC_PTE3	0x0000352C
#define CS35L41_MDSYNC_SYNC_MSM_STATUS	0x0000353C
#define CS35L41_BSTCVRT_VCTRL1		0x00003800
#define CS35L41_BSTCVRT_VCTRL2		0x00003804
#define CS35L41_BSTCVRT_PEAK_CUR	0x00003808
#define CS35L41_BSTCVRT_SFT_RAMP	0x0000380C
#define CS35L41_BSTCVRT_COEFF		0x00003810
#define CS35L41_BSTCVRT_SLOPE_LBST	0x00003814
#define CS35L41_BSTCVRT_SW_FREQ		0x00003818
#define CS35L41_BSTCVRT_DCM_CTRL	0x0000381C
#define CS35L41_BSTCVRT_DCM_MODE_FORCE	0x00003820
#define CS35L41_BSTCVRT_OVERVOLT_CTRL	0x00003830
#define CS35L41_VI_VOL_POL		0x00004000
#define CS35L41_VIMON_SPKMON_RESYNC	0x00004100
#define CS35L41_DTEMP_WARN_THLD		0x00004220
#define CS35L41_DTEMP_CFG		0x00004224
#define CS35L41_DTEMP_EN		0x00004308
#define CS35L41_VPVBST_FS_SEL		0x00004400
#define CS35L41_SP_ENABLES		0x00004800
#define CS35L41_SP_RATE_CTRL		0x00004804
#define CS35L41_SP_FORMAT		0x00004808
#define CS35L41_SP_HIZ_CTRL		0x0000480C
#define CS35L41_SP_FRAME_TX_SLOT	0x00004810
#define CS35L41_SP_FRAME_RX_SLOT	0x00004820
#define CS35L41_SP_TX_WL		0x00004830
#define CS35L41_SP_RX_WL		0x00004840
#define CS35L41_ASP_CONTROL4		0x00004854
#define CS35L41_DAC_PCM1_SRC		0x00004C00
#define CS35L41_ASP_TX1_SRC		0x00004C20
#define CS35L41_ASP_TX2_SRC		0x00004C24
#define CS35L41_ASP_TX3_SRC		0x00004C28
#define CS35L41_ASP_TX4_SRC		0x00004C2C
#define CS35L41_DSP1_RX1_SRC		0x00004C40
#define CS35L41_DSP1_RX2_SRC		0x00004C44
#define CS35L41_DSP1_RX3_SRC		0x00004C48
#define CS35L41_DSP1_RX4_SRC		0x00004C4C
#define CS35L41_DSP1_RX5_SRC		0x00004C50
#define CS35L41_DSP1_RX6_SRC		0x00004C54
#define CS35L41_DSP1_RX7_SRC		0x00004C58
#define CS35L41_DSP1_RX8_SRC		0x00004C5C
#define CS35L41_NGATE1_SRC		0x00004C60
#define CS35L41_NGATE2_SRC		0x00004C64
#define CS35L41_AMP_DIG_VOL_CTRL	0x00006000
#define CS35L41_VPBR_CFG		0x00006404
#define CS35L41_VBBR_CFG		0x00006408
#define CS35L41_VPBR_STATUS		0x0000640C
#define CS35L41_VBBR_STATUS		0x00006410
#define CS35L41_OVERTEMP_CFG		0x00006414
#define CS35L41_AMP_ERR_VOL		0x00006418
#define CS35L41_VOL_STATUS_TO_DSP	0x00006450
#define CS35L41_CLASSH_CFG		0x00006800
#define CS35L41_WKFET_CFG		0x00006804
#define CS35L41_NG_CFG			0x00006808
#define CS35L41_AMP_GAIN_CTRL		0x00006C04
#define CS35L41_DAC_MSM_CFG		0x00007400
#define CS35L41_IRQ1_CFG		0x00010000
#define CS35L41_IRQ1_STATUS		0x00010004
#define CS35L41_IRQ1_STATUS1		0x00010010
#define CS35L41_IRQ1_STATUS2		0x00010014
#define CS35L41_IRQ1_STATUS3		0x00010018
#define CS35L41_IRQ1_STATUS4		0x0001001C
#define CS35L41_IRQ1_RAW_STATUS1	0x00010090
#define CS35L41_IRQ1_RAW_STATUS2	0x00010094
#define CS35L41_IRQ1_RAW_STATUS3	0x00010098
#define CS35L41_IRQ1_RAW_STATUS4	0x0001009C
#define CS35L41_IRQ1_MASK1		0x00010110
#define CS35L41_IRQ1_MASK2		0x00010114
#define CS35L41_IRQ1_MASK3		0x00010118
#define CS35L41_IRQ1_MASK4		0x0001011C
#define CS35L41_IRQ1_FRC1		0x00010190
#define CS35L41_IRQ1_FRC2		0x00010194
#define CS35L41_IRQ1_FRC3		0x00010198
#define CS35L41_IRQ1_FRC4		0x0001019C
#define CS35L41_IRQ1_EDGE1		0x00010210
#define CS35L41_IRQ1_EDGE4		0x0001021C
#define CS35L41_IRQ1_POL1		0x00010290
#define CS35L41_IRQ1_POL2		0x00010294
#define CS35L41_IRQ1_POL3		0x00010298
#define CS35L41_IRQ1_POL4		0x0001029C
#define CS35L41_IRQ1_DB3		0x00010318
#define CS35L41_IRQ2_CFG		0x00010800
#define CS35L41_IRQ2_STATUS		0x00010804
#define CS35L41_IRQ2_STATUS1		0x00010810
#define CS35L41_IRQ2_STATUS2		0x00010814
#define CS35L41_IRQ2_STATUS3		0x00010818
#define CS35L41_IRQ2_STATUS4		0x0001081C
#define CS35L41_IRQ2_RAW_STATUS1	0x00010890
#define CS35L41_IRQ2_RAW_STATUS2	0x00010894
#define CS35L41_IRQ2_RAW_STATUS3	0x00010898
#define CS35L41_IRQ2_RAW_STATUS4	0x0001089C
#define CS35L41_IRQ2_MASK1		0x00010910
#define CS35L41_IRQ2_MASK2		0x00010914
#define CS35L41_IRQ2_MASK3		0x00010918
#define CS35L41_IRQ2_MASK4		0x0001091C
#define CS35L41_IRQ2_FRC1		0x00010990
#define CS35L41_IRQ2_FRC2		0x00010994
#define CS35L41_IRQ2_FRC3		0x00010998
#define CS35L41_IRQ2_FRC4		0x0001099C
#define CS35L41_IRQ2_EDGE1		0x00010A10
#define CS35L41_IRQ2_EDGE4		0x00010A1C
#define CS35L41_IRQ2_POL1		0x00010A90
#define CS35L41_IRQ2_POL2		0x00010A94
#define CS35L41_IRQ2_POL3		0x00010A98
#define CS35L41_IRQ2_POL4		0x00010A9C
#define CS35L41_IRQ2_DB3		0x00010B18
#define CS35L41_GPIO_STATUS1		0x00011000
#define CS35L41_GPIO1_CTRL1		0x00011008
#define CS35L41_GPIO2_CTRL1		0x0001100C
#define CS35L41_MIXER_NGATE_CFG		0x00012000
#define CS35L41_MIXER_NGATE_CH1_CFG	0x00012004
#define CS35L41_MIXER_NGATE_CH2_CFG	0x00012008
#define CS35L41_DSP_MBOX_1		0x00013000
#define CS35L41_DSP_MBOX_2		0x00013004
#define CS35L41_DSP_MBOX_3		0x00013008
#define CS35L41_DSP_MBOX_4		0x0001300C
#define CS35L41_DSP_MBOX_5		0x00013010
#define CS35L41_DSP_MBOX_6		0x00013014
#define CS35L41_DSP_MBOX_7		0x00013018
#define CS35L41_DSP_MBOX_8		0x0001301C
#define CS35L41_DSP_VIRT1_MBOX_1	0x00013020
#define CS35L41_DSP_VIRT1_MBOX_2	0x00013024
#define CS35L41_DSP_VIRT1_MBOX_3	0x00013028
#define CS35L41_DSP_VIRT1_MBOX_4	0x0001302C
#define CS35L41_DSP_VIRT1_MBOX_5	0x00013030
#define CS35L41_DSP_VIRT1_MBOX_6	0x00013034
#define CS35L41_DSP_VIRT1_MBOX_7	0x00013038
#define CS35L41_DSP_VIRT1_MBOX_8	0x0001303C
#define CS35L41_DSP_VIRT2_MBOX_1	0x00013040
#define CS35L41_DSP_VIRT2_MBOX_2	0x00013044
#define CS35L41_DSP_VIRT2_MBOX_3	0x00013048
#define CS35L41_DSP_VIRT2_MBOX_4	0x0001304C
#define CS35L41_DSP_VIRT2_MBOX_5	0x00013050
#define CS35L41_DSP_VIRT2_MBOX_6	0x00013054
#define CS35L41_DSP_VIRT2_MBOX_7	0x00013058
#define CS35L41_DSP_VIRT2_MBOX_8	0x0001305C
#define CS35L41_CLOCK_DETECT_1		0x00014000
#define CS35L41_TIMER1_CONTROL		0x00015000
#define CS35L41_TIMER1_COUNT_PRESET	0x00015004
#define CS35L41_TIMER1_START_STOP	0x0001500C
#define CS35L41_TIMER1_STATUS		0x00015010
#define CS35L41_TIMER1_COUNT_READBACK	0x00015014
#define CS35L41_TIMER1_DSP_CLK_CFG	0x00015018
#define CS35L41_TIMER1_DSP_CLK_STATUS	0x0001501C
#define CS35L41_TIMER2_CONTROL		0x00015100
#define CS35L41_TIMER2_COUNT_PRESET	0x00015104
#define CS35L41_TIMER2_START_STOP	0x0001510C
#define CS35L41_TIMER2_STATUS		0x00015110
#define CS35L41_TIMER2_COUNT_READBACK	0x00015114
#define CS35L41_TIMER2_DSP_CLK_CFG	0x00015118
#define CS35L41_TIMER2_DSP_CLK_STATUS	0x0001511C
#define CS35L41_DFT_JTAG_CONTROL	0x00016000
#define CS35L41_DIE_STS1		0x00017040
#define CS35L41_DIE_STS2		0x00017044
#define CS35L41_TEMP_CAL1		0x00017048
#define CS35L41_TEMP_CAL2		0x0001704C
#define CS35L41_DSP1_XMEM_PACK_0	0x02000000
#define CS35L41_DSP1_XMEM_PACK_3068	0x02002FF0
#define CS35L41_DSP1_XMEM_UNPACK32_0	0x02400000
#define CS35L41_DSP1_XMEM_UNPACK32_2046	0x02401FF8
#define CS35L41_DSP1_TIMESTAMP_COUNT	0x025C0800
#define CS35L41_DSP1_SYS_ID		0x025E0000
#define CS35L41_DSP1_SYS_VERSION	0x025E0004
#define CS35L41_DSP1_SYS_CORE_ID	0x025E0008
#define CS35L41_DSP1_SYS_AHB_ADDR	0x025E000C
#define CS35L41_DSP1_SYS_XSRAM_SIZE	0x025E0010
#define CS35L41_DSP1_SYS_YSRAM_SIZE	0x025E0018
#define CS35L41_DSP1_SYS_PSRAM_SIZE	0x025E0020
#define CS35L41_DSP1_SYS_PM_BOOT_SIZE	0x025E0028
#define CS35L41_DSP1_SYS_FEATURES	0x025E002C
#define CS35L41_DSP1_SYS_FIR_FILTERS	0x025E0030
#define CS35L41_DSP1_SYS_LMS_FILTERS	0x025E0034
#define CS35L41_DSP1_SYS_XM_BANK_SIZE	0x025E0038
#define CS35L41_DSP1_SYS_YM_BANK_SIZE	0x025E003C
#define CS35L41_DSP1_SYS_PM_BANK_SIZE	0x025E0040
#define CS35L41_DSP1_AHBM_WIN0_CTRL0	0x025E2000
#define CS35L41_DSP1_AHBM_WIN0_CTRL1	0x025E2004
#define CS35L41_DSP1_AHBM_WIN1_CTRL0	0x025E2008
#define CS35L41_DSP1_AHBM_WIN1_CTRL1	0x025E200C
#define CS35L41_DSP1_AHBM_WIN2_CTRL0	0x025E2010
#define CS35L41_DSP1_AHBM_WIN2_CTRL1	0x025E2014
#define CS35L41_DSP1_AHBM_WIN3_CTRL0	0x025E2018
#define CS35L41_DSP1_AHBM_WIN3_CTRL1	0x025E201C
#define CS35L41_DSP1_AHBM_WIN4_CTRL0	0x025E2020
#define CS35L41_DSP1_AHBM_WIN4_CTRL1	0x025E2024
#define CS35L41_DSP1_AHBM_WIN5_CTRL0	0x025E2028
#define CS35L41_DSP1_AHBM_WIN5_CTRL1	0x025E202C
#define CS35L41_DSP1_AHBM_WIN6_CTRL0	0x025E2030
#define CS35L41_DSP1_AHBM_WIN6_CTRL1	0x025E2034
#define CS35L41_DSP1_AHBM_WIN7_CTRL0	0x025E2038
#define CS35L41_DSP1_AHBM_WIN7_CTRL1	0x025E203C
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0	0x025E2040
#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1	0x025E2044
#define CS35L41_DSP1_XMEM_UNPACK24_0	0x02800000
#define CS35L41_DSP1_XMEM_UNPACK24_4093	0x02803FF4
#define CS35L41_DSP1_CTRL_BASE		0x02B80000
#define CS35L41_DSP1_CORE_SOFT_RESET	0x02B80010
#define CS35L41_DSP1_DEBUG		0x02B80040
#define CS35L41_DSP1_TIMER_CTRL		0x02B80048
#define CS35L41_DSP1_STREAM_ARB_CTRL	0x02B80050
#define CS35L41_DSP1_RX1_RATE		0x02B80080
#define CS35L41_DSP1_RX2_RATE		0x02B80088
#define CS35L41_DSP1_RX3_RATE		0x02B80090
#define CS35L41_DSP1_RX4_RATE		0x02B80098
#define CS35L41_DSP1_RX5_RATE		0x02B800A0
#define CS35L41_DSP1_RX6_RATE		0x02B800A8
#define CS35L41_DSP1_RX7_RATE		0x02B800B0
#define CS35L41_DSP1_RX8_RATE		0x02B800B8
#define CS35L41_DSP1_TX1_RATE		0x02B80280
#define CS35L41_DSP1_TX2_RATE		0x02B80288
#define CS35L41_DSP1_TX3_RATE		0x02B80290
#define CS35L41_DSP1_TX4_RATE		0x02B80298
#define CS35L41_DSP1_TX5_RATE		0x02B802A0
#define CS35L41_DSP1_TX6_RATE		0x02B802A8
#define CS35L41_DSP1_TX7_RATE		0x02B802B0
#define CS35L41_DSP1_TX8_RATE		0x02B802B8
#define CS35L41_DSP1_NMI_CTRL1		0x02B80480
#define CS35L41_DSP1_NMI_CTRL2		0x02B80488
#define CS35L41_DSP1_NMI_CTRL3		0x02B80490
#define CS35L41_DSP1_NMI_CTRL4		0x02B80498
#define CS35L41_DSP1_NMI_CTRL5		0x02B804A0
#define CS35L41_DSP1_NMI_CTRL6		0x02B804A8
#define CS35L41_DSP1_NMI_CTRL7		0x02B804B0
#define CS35L41_DSP1_NMI_CTRL8		0x02B804B8
#define CS35L41_DSP1_RESUME_CTRL	0x02B80500
#define CS35L41_DSP1_IRQ1_CTRL		0x02B80508
#define CS35L41_DSP1_IRQ2_CTRL		0x02B80510
#define CS35L41_DSP1_IRQ3_CTRL		0x02B80518
#define CS35L41_DSP1_IRQ4_CTRL		0x02B80520
#define CS35L41_DSP1_IRQ5_CTRL		0x02B80528
#define CS35L41_DSP1_IRQ6_CTRL		0x02B80530
#define CS35L41_DSP1_IRQ7_CTRL		0x02B80538
#define CS35L41_DSP1_IRQ8_CTRL		0x02B80540
#define CS35L41_DSP1_IRQ9_CTRL		0x02B80548
#define CS35L41_DSP1_IRQ10_CTRL		0x02B80550
#define CS35L41_DSP1_IRQ11_CTRL		0x02B80558
#define CS35L41_DSP1_IRQ12_CTRL		0x02B80560
#define CS35L41_DSP1_IRQ13_CTRL		0x02B80568
#define CS35L41_DSP1_IRQ14_CTRL		0x02B80570
#define CS35L41_DSP1_IRQ15_CTRL		0x02B80578
#define CS35L41_DSP1_IRQ16_CTRL		0x02B80580
#define CS35L41_DSP1_IRQ17_CTRL		0x02B80588
#define CS35L41_DSP1_IRQ18_CTRL		0x02B80590
#define CS35L41_DSP1_IRQ19_CTRL		0x02B80598
#define CS35L41_DSP1_IRQ20_CTRL		0x02B805A0
#define CS35L41_DSP1_IRQ21_CTRL		0x02B805A8
#define CS35L41_DSP1_IRQ22_CTRL		0x02B805B0
#define CS35L41_DSP1_IRQ23_CTRL		0x02B805B8
#define CS35L41_DSP1_SCRATCH1		0x02B805C0
#define CS35L41_DSP1_SCRATCH2		0x02B805C8
#define CS35L41_DSP1_SCRATCH3		0x02B805D0
#define CS35L41_DSP1_SCRATCH4		0x02B805D8
#define CS35L41_DSP1_CCM_CORE_CTRL	0x02BC1000
#define CS35L41_DSP1_CCM_CLK_OVERRIDE	0x02BC1008
#define CS35L41_DSP1_XM_MSTR_EN		0x02BC2000
#define CS35L41_DSP1_XM_CORE_PRI	0x02BC2008
#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI	0x02BC2010
#define CS35L41_DSP1_XM_AHB_UP_PL_PRI	0x02BC2018
#define CS35L41_DSP1_XM_ACCEL_PL0_PRI	0x02BC2020
#define CS35L41_DSP1_XM_NPL0_PRI	0x02BC2078
#define CS35L41_DSP1_YM_MSTR_EN		0x02BC20C0
#define CS35L41_DSP1_YM_CORE_PRI	0x02BC20C8
#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI	0x02BC20D0
#define CS35L41_DSP1_YM_AHB_UP_PL_PRI	0x02BC20D8
#define CS35L41_DSP1_YM_ACCEL_PL0_PRI	0x02BC20E0
#define CS35L41_DSP1_YM_NPL0_PRI	0x02BC2138
#define CS35L41_DSP1_PM_MSTR_EN		0x02BC2180
#define CS35L41_DSP1_PM_PATCH0_ADDR	0x02BC2188
#define CS35L41_DSP1_PM_PATCH0_EN	0x02BC218C
#define CS35L41_DSP1_PM_PATCH0_DATA_LO	0x02BC2190
#define CS35L41_DSP1_PM_PATCH0_DATA_HI	0x02BC2194
#define CS35L41_DSP1_PM_PATCH1_ADDR	0x02BC2198
#define CS35L41_DSP1_PM_PATCH1_EN	0x02BC219C
#define CS35L41_DSP1_PM_PATCH1_DATA_LO	0x02BC21A0
#define CS35L41_DSP1_PM_PATCH1_DATA_HI	0x02BC21A4
#define CS35L41_DSP1_PM_PATCH2_ADDR	0x02BC21A8
#define CS35L41_DSP1_PM_PATCH2_EN	0x02BC21AC
#define CS35L41_DSP1_PM_PATCH2_DATA_LO	0x02BC21B0
#define CS35L41_DSP1_PM_PATCH2_DATA_HI	0x02BC21B4
#define CS35L41_DSP1_PM_PATCH3_ADDR	0x02BC21B8
#define CS35L41_DSP1_PM_PATCH3_EN	0x02BC21BC
#define CS35L41_DSP1_PM_PATCH3_DATA_LO	0x02BC21C0
#define CS35L41_DSP1_PM_PATCH3_DATA_HI	0x02BC21C4
#define CS35L41_DSP1_PM_PATCH4_ADDR	0x02BC21C8
#define CS35L41_DSP1_PM_PATCH4_EN	0x02BC21CC
#define CS35L41_DSP1_PM_PATCH4_DATA_LO	0x02BC21D0
#define CS35L41_DSP1_PM_PATCH4_DATA_HI	0x02BC21D4
#define CS35L41_DSP1_PM_PATCH5_ADDR	0x02BC21D8
#define CS35L41_DSP1_PM_PATCH5_EN	0x02BC21DC
#define CS35L41_DSP1_PM_PATCH5_DATA_LO	0x02BC21E0
#define CS35L41_DSP1_PM_PATCH5_DATA_HI	0x02BC21E4
#define CS35L41_DSP1_PM_PATCH6_ADDR	0x02BC21E8
#define CS35L41_DSP1_PM_PATCH6_EN	0x02BC21EC
#define CS35L41_DSP1_PM_PATCH6_DATA_LO	0x02BC21F0
#define CS35L41_DSP1_PM_PATCH6_DATA_HI	0x02BC21F4
#define CS35L41_DSP1_PM_PATCH7_ADDR	0x02BC21F8
#define CS35L41_DSP1_PM_PATCH7_EN	0x02BC21FC
#define CS35L41_DSP1_PM_PATCH7_DATA_LO	0x02BC2200
#define CS35L41_DSP1_PM_PATCH7_DATA_HI	0x02BC2204
#define CS35L41_DSP1_MPU_XM_ACCESS0	0x02BC3000
#define CS35L41_DSP1_MPU_YM_ACCESS0	0x02BC3004
#define CS35L41_DSP1_MPU_WNDW_ACCESS0	0x02BC3008
#define CS35L41_DSP1_MPU_XREG_ACCESS0	0x02BC300C
#define CS35L41_DSP1_MPU_YREG_ACCESS0	0x02BC3014
#define CS35L41_DSP1_MPU_XM_ACCESS1	0x02BC3018
#define CS35L41_DSP1_MPU_YM_ACCESS1	0x02BC301C
#define CS35L41_DSP1_MPU_WNDW_ACCESS1	0x02BC3020
#define CS35L41_DSP1_MPU_XREG_ACCESS1	0x02BC3024
#define CS35L41_DSP1_MPU_YREG_ACCESS1	0x02BC302C
#define CS35L41_DSP1_MPU_XM_ACCESS2	0x02BC3030
#define CS35L41_DSP1_MPU_YM_ACCESS2	0x02BC3034
#define CS35L41_DSP1_MPU_WNDW_ACCESS2	0x02BC3038
#define CS35L41_DSP1_MPU_XREG_ACCESS2	0x02BC303C
#define CS35L41_DSP1_MPU_YREG_ACCESS2	0x02BC3044
#define CS35L41_DSP1_MPU_XM_ACCESS3	0x02BC3048
#define CS35L41_DSP1_MPU_YM_ACCESS3	0x02BC304C
#define CS35L41_DSP1_MPU_WNDW_ACCESS3	0x02BC3050
#define CS35L41_DSP1_MPU_XREG_ACCESS3	0x02BC3054
#define CS35L41_DSP1_MPU_YREG_ACCESS3	0x02BC305C
#define CS35L41_DSP1_MPU_XM_VIO_ADDR	0x02BC3100
#define CS35L41_DSP1_MPU_XM_VIO_STATUS	0x02BC3104
#define CS35L41_DSP1_MPU_YM_VIO_ADDR	0x02BC3108
#define CS35L41_DSP1_MPU_YM_VIO_STATUS	0x02BC310C
#define CS35L41_DSP1_MPU_PM_VIO_ADDR	0x02BC3110
#define CS35L41_DSP1_MPU_PM_VIO_STATUS	0x02BC3114
#define CS35L41_DSP1_MPU_LOCK_CONFIG