path: root/include/video/mach64.h

/*
 * ATI Mach64 Register Definitions
 *
 * Copyright (C) 1997 Michael AK Tesch
 *  written with much help from Jon Howell
 *
 * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
 *	
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

/*
 * most of the rest of this file comes from ATI sample code
 */
#ifndef REGMACH64_H
#define REGMACH64_H

/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */

/* Accelerator CRTC */
#define CRTC_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
#define CRTC2_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
#define CRTC_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
#define CRTC2_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
#define CRTC_H_SYNC_STRT	0x0004
#define CRTC2_H_SYNC_STRT	0x0004
#define CRTC_H_SYNC_DLY		0x0005
#define CRTC2_H_SYNC_DLY	0x0005
#define CRTC_H_SYNC_WID		0x0006
#define CRTC2_H_SYNC_WID	0x0006
#define CRTC_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
#define CRTC2_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
#define CRTC_V_TOTAL		0x0008
#define CRTC2_V_TOTAL		0x0008
#define CRTC_V_DISP		0x000A
#define CRTC2_V_DISP		0x000A
#define CRTC_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
#define CRTC2_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
#define CRTC_V_SYNC_STRT	0x000C
#define CRTC2_V_SYNC_STRT	0x000C
#define CRTC_V_SYNC_WID		0x000E
#define CRTC2_V_SYNC_WID	0x000E
#define CRTC_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
#define CRTC2_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
#define CRTC_OFF_PITCH		0x0014	/* Dword offset 0_05 */
#define CRTC_OFFSET		0x0014
#define CRTC_PITCH		0x0016
#define CRTC_INT_CNTL		0x0018	/* Dword offset 0_06 */
#define CRTC_GEN_CNTL		0x001C	/* Dword offset 0_07 */
#define CRTC_PIX_WIDTH		0x001D
#define CRTC_FIFO		0x001E
#define CRTC_EXT_DISP		0x001F

/* Memory Buffer Control */
#define DSP_CONFIG		0x0020	/* Dword offset 0_08 */
#define PM_DSP_CONFIG		0x0020	/* Dword offset 0_08 (Mobility Only) */
#define DSP_ON_OFF		0x0024	/* Dword offset 0_09 */
#define PM_DSP_ON_OFF		0x0024	/* Dword offset 0_09 (Mobility Only) */
#define TIMER_CONFIG		0x0028	/* Dword offset 0_0A */
#define MEM_BUF_CNTL		0x002C	/* Dword offset 0_0B */
#define MEM_ADDR_CONFIG		0x0034	/* Dword offset 0_0D */

/* Accelerator CRTC */
#define CRT_TRAP		0x0038	/* Dword offset 0_0E */

#define I2C_CNTL_0		0x003C	/* Dword offset 0_0F */

#define DSTN_CONTROL_LG		0x003C	/* Dword offset 0_0F (LG) */

/* Overscan */
#define OVR_CLR			0x0040	/* Dword offset 0_10 */
#define OVR2_CLR		0x0040	/* Dword offset 0_10 */
#define OVR_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
#define OVR2_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
#define OVR_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
#define OVR2_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */

/* Memory Buffer Control */
#define VGA_DSP_CONFIG		0x004C	/* Dword offset 0_13 */
#define PM_VGA_DSP_CONFIG	0x004C	/* Dword offset 0_13 (Mobility Only) */
#define VGA_DSP_ON_OFF		0x0050	/* Dword offset 0_14 */
#define PM_VGA_DSP_ON_OFF	0x0050	/* Dword offset 0_14 (Mobility Only) */
#define DSP2_CONFIG		0x0054	/* Dword offset 0_15 */
#define PM_DSP2_CONFIG		0x0054	/* Dword offset 0_15 (Mobility Only) */
#define DSP2_ON_OFF		0x0058	/* Dword offset 0_16 */
#define PM_DSP2_ON_OFF		0x0058	/* Dword offset 0_16 (Mobility Only) */

/* Accelerator CRTC */
#define CRTC2_OFF_PITCH		0x005C	/* Dword offset 0_17 */

/* Hardware Cursor */
#define CUR_CLR0		0x0060	/* Dword offset 0_18 */
#define CUR2_CLR0		0x0060	/* Dword offset 0_18 */
#define CUR_CLR1		0x0064	/* Dword offset 0_19 */
#define CUR2_CLR1		0x0064	/* Dword offset 0_19 */
#define CUR_OFFSET		0x0068	/* Dword offset 0_1A */
#define CUR2_OFFSET		0x0068	/* Dword offset 0_1A */
#define CUR_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
#define CUR2_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
#define CUR_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
#define CUR2_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */

#define CNFG_PANEL_LG		0x0074	/* Dword offset 0_1D (LG) */

/* General I/O Control */
#define GP_IO			0x0078	/* Dword offset 0_1E */

/* Test and Debug */
#define HW_DEBUG		0x007C	/* Dword offset 0_1F */

/* Scratch Pad and Test */
#define SCRATCH_REG0		0x0080	/* Dword offset 0_20 */
#define SCRATCH_REG1		0x0084	/* Dword offset 0_21 */
#define SCRATCH_REG2		0x0088	/* Dword offset 0_22 */
#define SCRATCH_REG3		0x008C	/* Dword offset 0_23 */

/* Clock Control */
#define CLOCK_CNTL			0x0090	/* Dword offset 0_24 */
/* CLOCK_CNTL register constants CT LAYOUT */
#define CLOCK_SEL			0x0f
#define CLOCK_SEL_INTERNAL		0x03
#define CLOCK_SEL_EXTERNAL		0x0c
#define CLOCK_DIV			0x30
#define CLOCK_DIV1			0x00
#define CLOCK_DIV2			0x10
#define CLOCK_DIV4			0x20
#define CLOCK_STROBE			0x40
/*  ?					0x80 */
/* CLOCK_CNTL register constants GX LAYOUT */
#define CLOCK_BIT			0x04	/* For ICS2595 */
#define CLOCK_PULSE			0x08	/* For ICS2595 */
/*#define CLOCK_STROBE			0x40 dito as CT */
#define CLOCK_DATA			0x80

/* For internal PLL(CT) start */
#define CLOCK_CNTL_ADDR			CLOCK_CNTL + 1
#define PLL_WR_EN			0x02
#define PLL_ADDR			0xfc
#define CLOCK_CNTL_DATA			CLOCK_CNTL + 2
#define PLL_DATA			0xff
/* For internal PLL(CT) end */

#define CLOCK_SEL_CNTL		0x0090	/* Dword offset 0_24 */

/* Configuration */
#define CNFG_STAT1		0x0094	/* Dword offset 0_25 */
#define CNFG_STAT2		0x0098	/* Dword offset 0_26 */

/* Bus Control */
#define BUS_CNTL		0x00A0	/* Dword offset 0_28 */

#define LCD_INDEX		0x00A4	/* Dword offset 0_29 */
#define LCD_DATA		0x00A8	/* Dword offset 0_2A */

#define HFB_PITCH_ADDR_LG	0x00A8	/* Dword offset 0_2A (LG) */

/* Memory Control */
#define EXT_MEM_CNTL		0x00AC	/* Dword offset 0_2B */
#define MEM_CNTL		0x00B0	/* Dword offset 0_2C */
#define MEM_VGA_WP_SEL		0x00B4	/* Dword offset 0_2D */
#define MEM_VGA_RP_SEL		0x00B8	/* Dword offset 0_2E */

#define I2C_CNTL_1		0x00BC	/* Dword offset 0_2F */

#define LT_GIO_LG		0x00BC	/* Dword offset 0_2F (LG) */

/* DAC Control */
#define DAC_REGS		0x00C0	/* Dword offset 0_30 */
#define DAC_W_INDEX		0x00C0	/* Dword offset 0_30 */
#define DAC_DATA		0x00C1	/* Dword offset 0_30 */
#define DAC_MASK		0x00C2	/* Dword offset 0_30 */
#define DAC_R_INDEX		0x00C3	/* Dword offset 0_30 */
#define DAC_CNTL		0x00C4	/* Dword offset 0_31 */

#define EXT_DAC_REGS		0x00C8	/* Dword offset 0_32 */

#define HORZ_STRETCHING_LG	0x00C8	/* Dword offset 0_32 (LG) */
#define VERT_STRETCHING_LG	0x00CC	/* Dword offset 0_33 (LG) */

/* Test and Debug */
#define GEN_TEST_CNTL		0x00D0	/* Dword offset 0_34 */

/* Custom Macros */
#define CUSTOM_MACRO_CNTL	0x00D4	/* Dword offset 0_35 */

#define LCD_GEN_CNTL_LG		0x00D4	/* Dword offset 0_35 (LG) */
#define POWER_MANAGEMENT_LG	0x00D8	/* Dword offset 0_36 (LG) */

/* Configuration */
#define CNFG_CNTL		0x00DC	/* Dword offset 0_37 (CT, ET, VT) */
#define CNFG_CHIP_ID		0x00E0	/* Dword offset 0_38 */
#define CNFG_STAT0		0x00E4	/* Dword offset 0_39 */

/* Test and Debug */
#define CRC_SIG			0x00E8	/* Dword offset 0_3A */
#define CRC2_SIG		0x00E8	/* Dword offset 0_3A */


/* GUI MEMORY MAPPED Registers */

/* Draw Engine Destination Trajectory */
#define DST_OFF_PITCH		0x0100	/* Dword offset 0_40 */
#define DST_X			0x0104	/* Dword offset 0_41 */
#define DST_Y			0x0108	/* Dword offset 0_42 */
#define DST_Y_X			0x010C	/* Dword offset 0_43 */
#define DST_WIDTH		0x0110	/* Dword offset 0_44 */
#define DST_HEIGHT		0x0114	/* Dword offset 0_45 */
#define DST_HEIGHT_WIDTH	0x0118	/* Dword offset 0_46 */
#define DST_X_WIDTH		0x011C	/* Dword offset 0_47 */
#define DST_BRES_LNTH		0x0120	/* Dword offset 0_48 */
#define DST_BRES_ERR		0x0124	/* Dword offset 0_49 */
#define DST_BRES_INC		0x0128	/* Dword offset 0_4A */
#define DST_BRES_DEC		0x012C	/* Dword offset 0_4B */
#define DST_CNTL		0x0130	/* Dword offset 0_4C */
#define DST_Y_X__ALIAS__	0x0134	/* Dword offset 0_4D */
#define TRAIL_BRES_ERR		0x0138	/* Dword offset 0_4E */
#define TRAIL_BRES_INC		0x013C	/* Dword offset 0_4F */
#define TRAIL_BRES_DEC		0x0140	/* Dword offset 0_50 */
#define LEAD_BRES_LNTH		0x0144	/* Dword offset 0_51 */
#define Z_OFF_PITCH		0x0148	/* Dword offset 0_52 */
#define Z_CNTL			0x014C	/* Dword offset 0_53 */
#define ALPHA_TST_CNTL		0x0150	/* Dword offset 0_54 */
#define SECONDARY_STW_EXP	0x0158	/* Dword offset 0_56 */
#define SECONDARY_S_X_INC	0x015C	/* Dword offset 0_57 */
#define SECONDARY_S_Y_INC	0x0160	/* Dword offset 0_58 */
#define SECONDARY_S_START	0x0164	/* Dword offset 0_59 */
#define SECONDARY_W_X_INC	0x0168	/* Dword offset 0_5A */
#define SECONDARY_W_Y_INC	0x016C	/* Dword offset 0_5B */
#define SECONDARY_W_START	0x0170	/* Dword offset 0_5C */
#define SECONDARY_T_X_INC	0x0174	/* Dword offset 0_5D */
#define SECONDARY_T_Y_INC	0x0178	/* Dword offset 0_5E */
#define SECONDARY_T_START	0x017C	/* Dword offset 0_5F */

/* Draw Engine Source Trajectory */
#define SRC_OFF_PITCH		0x0180	/* Dword offset 0_60 */
#define SRC_X			0x0184	/* Dword offset 0_61 */
#define SRC_Y			0x0188	/* Dword offset 0_62 */
#define SRC_Y_X			0x018C	/* Dword offset 0_63 */
#define SRC_WIDTH1		0x0190	/* Dword offset 0_64 */
#define SRC_HEIGHT1		0x0194	/* Dword offset 0_65 */
#define SRC_HEIGHT1_WIDTH1	0x0198	/* Dword offset 0_66 */
#define SRC_X_START		0x019C	/* Dword offset 0_67 */
#define SRC_Y_START		0x01A0	/* Dword offset 0_68 */
#define SRC_Y_X_START		0x01A4	/* Dword offset 0_69 */
#define SRC_WIDTH2		0x01A8	/* Dword offset 0_6A */
#define SRC_HEIGHT2		0x01AC	/* Dword offset 0_6B */
#define SRC_HEIGHT2_WIDTH2	0x01B0	/* Dword offset 0_6C */
#define SRC_CNTL		0x01B4	/* Dword offset 0_6D */

#define SCALE_OFF		0x01C0	/* Dword offset 0_70 */
#define SECONDARY_SCALE_OFF	0x01C4	/* Dword offset 0_71 */

#define TEX_0_OFF		0x01C0	/* Dword offset 0_70 */
#define TEX_1_OFF		0x01C4	/* Dword offset 0_71 */
#define TEX_2_OFF		0x01C8	/* Dword offset 0_72 */
#define TEX_3_OFF		0x01CC	/* Dword offset 0_73 */
#define TEX_4_OFF		0x01D0	/* Dword offset 0_74 */
#define TEX_5_OFF		0x01D4	/* Dword offset 0_75 */
#define TEX_6_OFF		0x01D8	/* Dword offset 0_76 */
#define TEX_7_OFF		0x01DC	/* Dword offset 0_77 */

#define SCALE_WIDTH		0x01DC	/* Dword offset 0_77 */
#define SCALE_HEIGHT		0x01E0	/* Dword offset 0_78 */

#define TEX_8_OFF		0x01E0	/* Dword offset 0_78 */
#define TEX_9_OFF		0x01E4	/* Dword offset 0_79 */
#define TEX_10_OFF		0x01E8	/* Dword offset 0_7A */
#define S_Y_INC			0x01EC	/* Dword offset 0_7B */

#define SCALE_PITCH		0x01EC	/* Dword offset 0_7B */
#define SCALE_X_INC		0x01F0	/* Dword offset 0_7C */

#define RED_X_INC		0x01F0	/* Dword offset 0_7C */
#define GREEN_X_INC		0x01F4	/* Dword offset 0_7D */

#define SCALE_Y_INC		0x01F4	/* Dword offset 0_7D */
#define SCALE_VACC		0x01F8	/* Dword offset 0_7E */
#define SCALE_3D_CNTL		0x01FC	/* Dword offset 0_7F */

/* Host Data */
#define HOST_DATA0		0x0200	/* Dword offset 0_80 */
#define HOST_DATA1		0x0204	/* Dword offset 0_81 */
#define HOST_DATA2		0x0208	/* Dword offset 0_82 */
#define HOST_DATA3		0x020C	/* Dword offset 0_83 */
#define HOST_DATA4		0x0210	/* Dword offset 0_84 */
#define HOST_DATA5		0x0214	/* Dword offset 0_85 */
#define HOST_DATA6		0x0218	/* Dword offset 0_86 */
#define HOST_DATA7		0x021C	/* Dword offset 0_87 */
#define HOST_DATA8		0x0220	/* Dword offset 0_88 */
#define HOST_DATA9		0x0224	/* Dword offset 0_89 */
#define HOST_DATAA		0x0228	/* Dword offset 0_8A */
#define HOST_DATAB		0x022C	/* Dword offset 0_8B */
#define HOST_DATAC		0x0230	/* Dword offset 0_8C */
#define HOST_DATAD		0x0234	/* Dword offset 0_8D */
#define HOST_DATAE		0x0238	/* Dword offset 0_8E */
#define HOST_DATAF		0x023C	/* Dword offset 0_8F */
#define HOST_CNTL		0x0240	/* Dword offset 0_90 */

/* GUI Bus Mastering */
#define BM_HOSTDATA		0x0244	/* Dword offset 0_91 */
#define BM_ADDR			0x0248	/* Dword offset 0_92 */
#define BM_DATA			0x0248	/* Dword offset 0_92 */
#define BM_GUI_TABLE_CMD	0x024C	/* Dword offset 0_93 */

/* Pattern */
#define PAT_REG0		0x0280	/* Dword offset 0_A0 */
#define PAT_REG1		0x0284	/* Dword offset 0_A1 */
#define PAT_CNTL		0x0288	/* Dword offset 0_A2 */

/* Scissors */
#define SC_LEFT			0x02A0	/* Dword offset 0_A8 */
#define SC_RIGHT		0x02A4	/* Dword offset 0_A9 */
#define SC_LEFT_RIGHT		0x02A8	/* Dword offset 0_AA */
#define SC_TOP			0x02AC	/* Dword offset 0_AB */
#define SC_BOTTOM		0x02B0	/* Dword offset 0_AC */
#define SC_TOP_BOTTOM		0x02B4	/* Dword offset 0_AD */

/* Data Path */
#define USR1_DST_OFF_PITCH	0x02B8	/* Dword offset 0_AE */
#define USR2_DST_OFF_PITCH	0x02BC	/* Dword offset 0_AF */
#define DP_BKGD_CLR		0x02C0	/* Dword offset 0_B0 */
#define DP_FOG_CLR		0x02C4	/* Dword offset 0_B1 */
#define DP_FRGD_CLR		0x02C4	/* Dword offset 0_B1 */
#define DP_WRITE_MASK		0x02C8	/* Dword offset 0_B2 */
#define DP_CHAIN_MASK		0x02CC	/* Dword offset 0_B3 */
#define DP_PIX_WIDTH		0x02D0	/* Dword offset 0_B4 */
#define DP_MIX			0x02D4	/* Dword offset 0_B5 */
#define DP_SRC			0x02D8	/* Dword offset 0_B6 */
#define DP_FRGD_CLR_MIX		0x02DC	/* Dword offset 0_B7 */
#define DP_FRGD_BKGD_CLR	0x02E0	/* Dword offset 0_B8 */

/* Draw Engine Destination Trajectory */
#define DST_X_Y			0x02E8	/* Dword offset 0_BA */
#define DST_WIDTH_HEIGHT	0x02EC	/* Dword offset 0_BB */

/* Data Path */
#define USR_DST_PICTH		0x02F0	/* Dword offset 0_BC */
#define DP_SET_GUI_ENGINE2	0x02F8	/* Dword offset 0_BE */
#define DP_SET_GUI_ENGINE	0x02FC	/* Dword offset 0_BF */

/* Color Compare */
#define CLR_CMP_CLR		0x0300	/* Dword offset 0_C0 */
#define CLR_CMP_MASK		0x0304	/* Dword offset 0_C1 */
#define CLR_CMP_CNTL		0x0308	/* Dword offset 0_C2 */

/* Command FIFO */
#define FIFO_STAT		0x0310