path: root/sound/soc/amd/include/acp_2_2_d.h

/*
 * ACP_2_2 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef ACP_2_2_D_H
#define ACP_2_2_D_H

#define mmACP_DMA_CNTL_0                                                        0x5000
#define mmACP_DMA_CNTL_1                                                        0x5001
#define mmACP_DMA_CNTL_2                                                        0x5002
#define mmACP_DMA_CNTL_3                                                        0x5003
#define mmACP_DMA_CNTL_4                                                        0x5004
#define mmACP_DMA_CNTL_5                                                        0x5005
#define mmACP_DMA_CNTL_6                                                        0x5006
#define mmACP_DMA_CNTL_7                                                        0x5007
#define mmACP_DMA_CNTL_8                                                        0x5008
#define mmACP_DMA_CNTL_9                                                        0x5009
#define mmACP_DMA_CNTL_10                                                       0x500a
#define mmACP_DMA_CNTL_11                                                       0x500b
#define mmACP_DMA_CNTL_12                                                       0x500c
#define mmACP_DMA_CNTL_13                                                       0x500d
#define mmACP_DMA_CNTL_14                                                       0x500e
#define mmACP_DMA_CNTL_15                                                       0x500f
#define mmACP_DMA_DSCR_STRT_IDX_0                                               0x5010
#define mmACP_DMA_DSCR_STRT_IDX_1                                               0x5011
#define mmACP_DMA_DSCR_STRT_IDX_2                                               0x5012
#define mmACP_DMA_DSCR_STRT_IDX_3                                               0x5013
#define mmACP_DMA_DSCR_STRT_IDX_4                                               0x5014
#define mmACP_DMA_DSCR_STRT_IDX_5                                               0x5015
#define mmACP_DMA_DSCR_STRT_IDX_6                                               0x5016
#define mmACP_DMA_DSCR_STRT_IDX_7                                               0x5017
#define mmACP_DMA_DSCR_STRT_IDX_8                                               0x5018
#define mmACP_DMA_DSCR_STRT_IDX_9                                               0x5019
#define mmACP_DMA_DSCR_STRT_IDX_10                                              0x501a
#define mmACP_DMA_DSCR_STRT_IDX_11                                              0x501b
#define mmACP_DMA_DSCR_STRT_IDX_12                                              0x501c
#define mmACP_DMA_DSCR_STRT_IDX_13                                              0x501d
#define mmACP_DMA_DSCR_STRT_IDX_14                                              0x501e
#define mmACP_DMA_DSCR_STRT_IDX_15                                              0x501f
#define mmACP_DMA_DSCR_CNT_0                                                    0x5020
#define mmACP_DMA_DSCR_CNT_1                                                    0x5021
#define mmACP_DMA_DSCR_CNT_2                                                    0x5022
#define mmACP_DMA_DSCR_CNT_3                                                    0x5023
#define mmACP_DMA_DSCR_CNT_4                                                    0x5024
#define mmACP_DMA_DSCR_CNT_5                                                    0x5025
#define mmACP_DMA_DSCR_CNT_6                                                    0x5026
#define mmACP_DMA_DSCR_CNT_7                                                    0x5027
#define mmACP_DMA_DSCR_CNT_8                                                    0x5028
#define mmACP_DMA_DSCR_CNT_9                                                    0x5029
#define mmACP_DMA_DSCR_CNT_10                                                   0x502a
#define mmACP_DMA_DSCR_CNT_11                                                   0x502b
#define mmACP_DMA_DSCR_CNT_12                                                   0x502c
#define mmACP_DMA_DSCR_CNT_13                                                   0x502d
#define mmACP_DMA_DSCR_CNT_14                                                   0x502e
#define mmACP_DMA_DSCR_CNT_15                                                   0x502f
#define mmACP_DMA_PRIO_0                                                        0x5030
#define mmACP_DMA_PRIO_1                                                        0x5031
#define mmACP_DMA_PRIO_2                                                        0x5032
#define mmACP_DMA_PRIO_3                                                        0x5033
#define mmACP_DMA_PRIO_4                                                        0x5034
#define mmACP_DMA_PRIO_5                                                        0x5035
#define mmACP_DMA_PRIO_6                                                        0x5036
#define mmACP_DMA_PRIO_7                                                        0x5037
#define mmACP_DMA_PRIO_8                                                        0x5038
#define mmACP_DMA_PRIO_9                                                        0x5039
#define mmACP_DMA_PRIO_10                                                       0x503a
#define mmACP_DMA_PRIO_11                                                       0x503b
#define mmACP_DMA_PRIO_12                                                       0x503c
#define mmACP_DMA_PRIO_13                                                       0x503d
#define mmACP_DMA_PRIO_14                                                       0x503e
#define mmACP_DMA_PRIO_15                                                       0x503f
#define mmACP_DMA_CUR_DSCR_0                                                    0x5040
#define mmACP_DMA_CUR_DSCR_1                                                    0x5041
#define mmACP_DMA_CUR_DSCR_2                                                    0x5042
#define mmACP_DMA_CUR_DSCR_3                                                    0x5043
#define mmACP_DMA_CUR_DSCR_4                                                    0x5044
#define mmACP_DMA_CUR_DSCR_5                                                    0x5045
#define mmACP_DMA_CUR_DSCR_6                                                    0x5046
#define mmACP_DMA_CUR_DSCR_7                                                    0x5047
#define mmACP_DMA_CUR_DSCR_8                                                    0x5048
#define mmACP_DMA_CUR_DSCR_9                                                    0x5049
#define mmACP_DMA_CUR_DSCR_10                                                   0x504a
#define mmACP_DMA_CUR_DSCR_11                                                   0x504b
#define mmACP_DMA_CUR_DSCR_12                                                   0x504c
#define mmACP_DMA_CUR_DSCR_13                                                   0x504d
#define mmACP_DMA_CUR_DSCR_14                                                   0x504e
#define mmACP_DMA_CUR_DSCR_15                                                   0x504f
#define mmACP_DMA_CUR_TRANS_CNT_0                                               0x5050
#define mmACP_DMA_CUR_TRANS_CNT_1                                               0x5051
#define mmACP_DMA_CUR_TRANS_CNT_2                                               0x5052
#define mmACP_DMA_CUR_TRANS_CNT_3                                               0x5053
#define mmACP_DMA_CUR_TRANS_CNT_4                                               0x5054
#define mmACP_DMA_CUR_TRANS_CNT_5                                               0x5055
#define mmACP_DMA_CUR_TRANS_CNT_6                                               0x5056
#define mmACP_DMA_CUR_TRANS_CNT_7                                               0x5057
#define mmACP_DMA_CUR_TRANS_CNT_8                                               0x5058
#define mmACP_DMA_CUR_TRANS_CNT_9                                               0x5059
#define mmACP_DMA_CUR_TRANS_CNT_10                                              0x505a
#define mmACP_DMA_CUR_TRANS_CNT_11                                              0x505b
#define mmACP_DMA_CUR_TRANS_CNT_12                                              0x505c
#define mmACP_DMA_CUR_TRANS_CNT_13                                              0x505d
#define mmACP_DMA_CUR_TRANS_CNT_14                                              0x505e
#define mmACP_DMA_CUR_TRANS_CNT_15                                              0x505f
#define mmACP_DMA_ERR_STS_0                                                     0x5060
#define mmACP_DMA_ERR_STS_1                                                     0x5061
#define mmACP_DMA_ERR_STS_2                                                     0x5062
#define mmACP_DMA_ERR_STS_3                                                     0x5063
#define mmACP_DMA_ERR_STS_4                                                     0x5064
#define mmACP_DMA_ERR_STS_5                                                     0x5065
#define mmACP_DMA_ERR_STS_6                                                     0x5066
#define mmACP_DMA_ERR_STS_7                                                     0x5067
#define mmACP_DMA_ERR_STS_8                                                     0x5068
#define mmACP_DMA_ERR_STS_9                                                     0x5069
#define mmACP_DMA_ERR_STS_10                                                    0x506a
#define mmACP_DMA_ERR_STS_11                                                    0x506b
#define mmACP_DMA_ERR_STS_12                                                    0x506c
#define mmACP_DMA_ERR_STS_13                                                    0x506d
#define mmACP_DMA_ERR_STS_14                                                    0x506e
#define mmACP_DMA_ERR_STS_15                                                    0x506f
#define mmACP_DMA_DESC_BASE_ADDR                                                0x5070
#define mmACP_DMA_DESC_MAX_NUM_DSCR                                             0x5071
#define mmACP_DMA_CH_STS                                                        0x5072
#define mmACP_DMA_CH_GROUP                                                      0x5073
#define mmACP_DSP0_CACHE_OFFSET0                                                0x5078
#define mmACP_DSP0_CACHE_SIZE0                                                  0x5079
#define mmACP_DSP0_CACHE_OFFSET1                                                0x507a
#define mmACP_DSP0_CACHE_SIZE1                                                  0x507b
#define mmACP_DSP0_CACHE_OFFSET2                                                0x507c
#define mmACP_DSP0_CACHE_SIZE2                                                  0x507d
#define mmACP_DSP0_CACHE_OFFSET3                                                0x507e
#define mmACP_DSP0_CACHE_SIZE3                                                  0x507f
#define mmACP_DSP0_CACHE_OFFSET4                                                0x5080
#define mmACP_DSP0_CACHE_SIZE4                                                  0x5081
#define mmACP_DSP0_CACHE_OFFSET5                                                0x5082
#define mmACP_DSP0_CACHE_SIZE5                                                  0x5083
#define mmACP_DSP0_CACHE_OFFSET6                                                0x5084
#define mmACP_DSP0_CACHE_SIZE6                                                  0x5085
#define mmACP_DSP0_CACHE_OFFSET7                                                0x5086
#define mmACP_DSP0_CACHE_SIZE7                                                  0x5087
#define mmACP_DSP0_CACHE_OFFSET8                                                0x5088
#define mmACP_DSP0_CACHE_SIZE8                                                  0x5089
#define mmACP_DSP0_NONCACHE_OFFSET0                                             0x508a
#define mmACP_DSP0_NONCACHE_SIZE0                                               0x508b
#define mmACP_DSP0_NONCACHE_OFFSET1                                             0x508c
#define mmACP_DSP0_NONCACHE_SIZE1                                               0x508d
#define mmACP_DSP0_DEBUG_PC                                                     0x508e
#define mmACP_DSP0_NMI_SEL                                                      0x508f
#define mmACP_DSP0_CLKRST_CNTL                                                  0x5090
#define mmACP_DSP0_RUNSTALL                                                     0x5091
#define mmACP_DSP0_OCD_HALT_ON_RST                                              0x5092
#define mmACP_DSP0_WAIT_MODE                                                    0x5093
#define mmACP_DSP0_VECT_SEL                                                     0x5094
#define mmACP_DSP0_DEBUG_REG1                                                   0x5095
#define mmACP_DSP0_DEBUG_REG2                                                   0x5096
#define mmACP_DSP0_DEBUG_REG3                                                   0x5097
#define mmACP_DSP1_CACHE_OFFSET0                                                0x509d
#define mmACP_DSP1_CACHE_SIZE0                                                  0x509e
#define mmACP_DSP1_CACHE_OFFSET1                                                0x509f
#define mmACP_DSP1_CACHE_SIZE1                                                  0x50a0
#define mmACP_DSP1_CACHE_OFFSET2                                                0x50a1
#define mmACP_DSP1_CACHE_SIZE2                                                  0x50a2
#define mmACP_DSP1_CACHE_OFFSET3                                                0x50a3
#define mmACP_DSP1_CACHE_SIZE3                                                  0x50a4
#define mmACP_DSP1_CACHE_OFFSET4                                                0x50a5
#define mmACP_DSP1_CACHE_SIZE4                                                  0x50a6
#define mmACP_DSP1_CACHE_OFFSET5                                                0x50a7
#define mmACP_DSP1_CACHE_SIZE5                                                  0x50a8
#define mmACP_DSP1_CACHE_OFFSET6                                                0x50a9
#define mmACP_DSP1_CACHE_SIZE6                                                  0x50aa
#define mmACP_DSP1_CACHE_OFFSET7                                                0x50ab
#define mmACP_DSP1_CACHE_SIZE7                                                  0x50ac
#define mmACP_DSP1_CACHE_OFFSET8                                                0x50ad
#define mmACP_DSP1_CACHE_SIZE8                                                  0x50ae
#define mmACP_DSP1_NONCACHE_OFFSET0                                             0x50af
#define mmACP_DSP1_NONCACHE_SIZE0                                               0x50b0
#define mmACP_DSP1_NONCACHE_OFFSET1                                             0x50b1
#define mmACP_DSP1_NONCACHE_SIZE1                                               0x50b2
#define mmACP_DSP1_DEBUG_PC                                                     0x50b3
#define mmACP_DSP1_NMI_SEL                                                      0x50b4
#define mmACP_DSP1_CLKRST_CNTL                                                  0x50b5
#define mmACP_DSP1_RUNSTALL                                                     0x50b6
#define mmACP_DSP1_OCD_HALT_ON_RST                                              0x50b7
#define mmACP_DSP1_WAIT_MODE                                                    0x50b8
#define mmACP_DSP1_VECT_SEL                                                     0x50b9
#define mmACP_DSP1_DEBUG_REG1                                                   0x50ba
#define mmACP_DSP1_DEBUG_REG2                                                   0x50bb
#define mmACP_DSP1_DEBUG_REG3                                                   0x50bc
#define mmACP_DSP2_CACHE_OFFSET0                                                0x50c2
#define mmACP_DSP2_CACHE_SIZE0                                                  0x50c3
#define mmACP_DSP2_CACHE_OFFSET1                                                0x50c4
#define mmACP_DSP2_CACHE_SIZE1                                                  0x50c5
#define mmACP_DSP2_CACHE_OFFSET2                                                0x50c6
#define mmACP_DSP2_CACHE_SIZE2                                                  0x50c7
#define mmACP_DSP2_CACHE_OFFSET3                                                0x50c8
#define mmACP_DSP2_CACHE_SIZE3                                                  0x50c9
#define mmACP_DSP2_CACHE_OFFSET4                                                0x50ca
#define mmACP_DSP2_CACHE_SIZE4                                                  0x50cb
#define mmACP_DSP2_CACHE_OFFSET5                                                0x50cc
#define mmACP_DSP2_CACHE_SIZE5                                                  0x50cd
#define mmACP_DSP2_CACHE_OFFSET6                                                0x50ce
#define mmACP_DSP2_CACHE_SIZE6                                                  0x50cf
#define mmACP_DSP2_CACHE_OFFSET7                                                0x50d0
#define mmACP_DSP2_CACHE_SIZE7                                                  0x50d1
#define mmACP_DSP2_CACHE_OFFSET8                                                0x50d2
#define mmACP_DSP2_CACHE_SIZE8                                                  0x50d3
#define mmACP_DSP2_NONCACHE_OFFSET0                                             0x50d4
#define mmACP_DSP2_NONCACHE_SIZE0                                               0x50d5
#define mmACP_DSP2_NONCACHE_OFFSET1                                             0x50d6
#define mmACP_DSP2_NONCACHE_SIZE1                                               0x50d7
#define mmACP_DSP2_DEBUG_PC                                                     0x50d8
#define mmACP_DSP2_NMI_SEL                                                      0x50d9
#define mmACP_DSP2_CLKRST_CNTL                                                  0x50da
#define mmACP_DSP2_RUNSTALL                                                     0x50db
#define mmACP_DSP2_OCD_HALT_ON_RST                                              0x50dc
#define mmACP_DSP2_WAIT_MODE                                                    0x50dd
#define mmACP_DSP2_VECT_SEL                                                     0x50de
#define mmACP_DSP2_DEBUG_REG1                                                   0x50df
#define mmACP_DSP2_DEBUG_REG2                                                   0x50e0
#define mmACP_DSP2_DEBUG_REG3                                                   0x50e1
#define mmACP_AXI2DAGB_ONION_CNTL                                               0x50e7
#define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR                                      0x50e8
#define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD                                      0x50e9
#define mmACP_DAGB_Onion_TransPerf_Counter_Control                              0x50ea
#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current                           0x50eb
#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak                              0x50ec
#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current                           0x50ed
#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak                              0x50ee
#define mmACP_AXI2DAGB_GARLIC_CNTL                                              0x50f3
#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR                                     0x50f4
#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD                                     0x50f5
#define mmACP_DAGB_Garlic_TransPerf_Counter_Control                             0x50f6
#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current                          0x50f7
#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak                             0x50f8
#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current                          0x50f9
#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak                             0x50fa
#define mmACP_DAGB_PAGE_SIZE_GRP_1                                              0x50ff
#define mmACP_DAGB_BASE_ADDR_GRP_1                                              0x5100
#define mmACP_DAGB_PAGE_SIZE_GRP_2                                              0x5101
#define mmACP_DAGB_BASE_ADDR_GRP_2                                              0x5102
#define mmACP_DAGB_PAGE_SIZE_GRP_3                                              0x5103
#define mmACP_DAGB_BASE_ADDR_GRP_3                                              0x5104
#define mmACP_DAGB_PAGE_SIZE_GRP_4                                              0x5105
#define mmACP_DAGB_BASE_ADDR_GRP_4                                              0x5106
#define mmACP_DAGB_PAGE_SIZE_GRP_5                                              0x5107
#define mmACP_DAGB_BASE_ADDR_GRP_5                                              0x5108
#define mmACP_DAGB_PAGE_SIZE_GRP_6                                              0x5109
#define mmACP_DAGB_BASE_ADDR_GRP_6                                              0x510a
#define mmACP_DAGB_PAGE_SIZE_GRP_7                                              0x510b
#define mmACP_DAGB_BASE_ADDR_GRP_7                                              0x510c
#define mmACP_DAGB_PAGE_SIZE_GRP_8                                              0x510d
#define mmACP_DAGB_BASE_ADDR_GRP_8                                              0x510e
#define mmACP_DAGB_ATU_CTRL                                                     0x510f
#define mmACP_CONTROL                                                           0x5131
#define mmACP_STATUS                                                            0x5133
#define mmACP_SOFT_RESET                                                        0x5134
#define mmACP_PwrMgmt_CNTL                                                      0x5135
#define mmACP_CAC_INDICATOR_CONTROL                                             0x5136
#define mmACP_SMU_MAILBOX                                                       0x5137
#define mmACP_FUTURE_REG_SCLK_0                                                 0x5138
#define mmACP_FUTURE_REG_SCLK_1                                                 0x5139
#define mmACP_FUTURE_REG_SCLK_2                                                 0x513a
#define mmACP_FUTURE_REG_SCLK_3                                                 0x513b
#define mmACP_FUTURE_REG_SCLK_4                                                 0x513c
#define mmACP_DAGB_DEBUG_CNT_ENABLE                                             0x513d
#define mmACP_DAGBG_WR_ASK_CNT                                                  0x513e
#define mmACP_DAGBG_WR_GO_CNT                                                   0x513f
#define mmACP_DAGBG_WR_EXP_RESP_CNT                                             0x5140
#define mmACP_DAGBG_WR_ACTUAL_RESP_CNT                                          0x5141
#define mmACP_DAGBG_RD_ASK_CNT                                                  0x5142
#define mmACP_DAGBG_RD_GO_CNT                                                   0x5143
#define mmACP_DAGBG_RD_EXP_RESP_CNT                                             0x5144
#define mmACP_DAGBG_RD_ACTUAL_RESP_CNT                                          0x5145
#define mmACP_DAGBO_WR_ASK_CNT                                                  0x5146
#define mmACP_DAGBO_WR_GO_CNT                                                   0x5147
#define mmACP_DAGBO_WR_EXP_RESP_CNT                                             0x5148
#define mmACP_DAGBO_WR_ACTUAL_RESP_CNT                                          0x5149
#define mmACP_DAGBO_RD_ASK_CNT                                                  0x514a
#define mmACP_DAGBO_RD_GO_CNT                                                   0x514b
#define mmACP_DAGBO_RD_EXP_RESP_CNT                                             0x514c
#define mmACP_DAGBO_RD_ACTUAL_RESP_CNT                                          0x514d
#define mmACP_BRB_CONTROL                                                       0x5156
#define mmACP_EXTERNAL_INTR_ENB                                                 0x5157
#define mmACP_EXTERNAL_INTR_CNTL                                                0x5158
#define mmACP_ERROR_SOURCE_STS                                                  0x5159
#define mmACP_DSP_SW_INTR_TRIG                                                  0x515a
#define mmACP_DSP_SW_INTR_CNTL                                                  0x515b
#define mmACP_DAGBG_TIMEOUT_CNTL                                                0x515c
#define mmACP_DAGBO_TIMEOUT_CNTL                                                0x515d
#define mmACP_EXTERNAL_INTR_STAT                                                0x515e
#define mmACP_DSP_SW_INTR_STAT                                                  0x515f
#define mmACP_DSP0_INTR_CNTL                                                    0x5160
#define mmACP_DSP0_INTR_STAT                                                    0x5161
#define mmACP_DSP0_TIMEOUT_CNTL                                                 0x5162
#define mmACP_DSP1_INTR_CNTL                                                    0x5163
#define mmACP_DSP1_INTR_STAT                                                    0x5164
#define mmACP_DSP1_TIMEOUT_CNTL                                                 0x5165
#define mmACP_DSP2_INTR_CNTL                                                    0x5166
#define mmACP_DSP2_INTR_STAT                                                    0x5167
#define mmACP_DSP2_TIMEOUT_CNTL                                                 0x5168
#define mmACP_DSP0_EXT_TIMER_CNTL                                               0x5169
#define mmACP_DSP1_EXT_TIMER_CNTL                                               0x516a
#define mmACP_DSP2_EXT_TIMER_CNTL                                               0x516b
#define mmACP_AXI2DAGB_SEM_0                                                    0x516c
#define mmACP_AXI2DAGB_SEM_1                                                    0x516d
#define mmACP_AXI2DAGB_SEM_2                                                    0x516e
#define mmACP_AXI2DAGB_SEM_3                                                    0x516f
#define mmACP_AXI2DAGB_SEM_4                                                    0x5170
#define mmACP_AXI2DAGB_SEM_5                                                    0x5171
#define mmACP_AXI2DAGB_SEM_6                                                    0x5172
#define mmACP_AXI2DAGB_SEM_7                                                    0x5173
#define mmACP_AXI2DAGB_SEM_8                                                    0x5174
#define mmACP_AXI2DAGB_SEM_9                                                    0x5175
#define mmACP_AXI2DAGB_SEM_10                                                   0x5176
#define mmACP_AXI2DAGB_SEM_11                                                   0x5177
#define mmACP_AXI2DAGB_SEM_12                                                   0x5178
#define mmACP_AXI2DAGB_SEM_13                                                   0x5179
#define mmACP_AXI2DAGB_SEM_14                                                   0x517a
#define mmACP_AXI2DAGB_SEM_15