path: root/sound/soc/atmel/mchp-i2s-mcc.c

// SPDX-License-Identifier: GPL-2.0
//
// Driver for Microchip I2S Multi-channel controller
//
// Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
//
// Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/slab.h>

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/lcm.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

/*
 * ---- I2S Controller Register map ----
 */
#define MCHP_I2SMCC_CR		0x0000	/* Control Register */
#define MCHP_I2SMCC_MRA		0x0004	/* Mode Register A */
#define MCHP_I2SMCC_MRB		0x0008	/* Mode Register B */
#define MCHP_I2SMCC_SR		0x000C	/* Status Register */
#define MCHP_I2SMCC_IERA	0x0010	/* Interrupt Enable Register A */
#define MCHP_I2SMCC_IDRA	0x0014	/* Interrupt Disable Register A */
#define MCHP_I2SMCC_IMRA	0x0018	/* Interrupt Mask Register A */
#define MCHP_I2SMCC_ISRA	0X001C	/* Interrupt Status Register A */

#define MCHP_I2SMCC_IERB	0x0020	/* Interrupt Enable Register B */
#define MCHP_I2SMCC_IDRB	0x0024	/* Interrupt Disable Register B */
#define MCHP_I2SMCC_IMRB	0x0028	/* Interrupt Mask Register B */
#define MCHP_I2SMCC_ISRB	0X002C	/* Interrupt Status Register B */

#define MCHP_I2SMCC_RHR		0x0030	/* Receiver Holding Register */
#define MCHP_I2SMCC_THR		0x0034	/* Transmitter Holding Register */

#define MCHP_I2SMCC_RHL0R	0x0040	/* Receiver Holding Left 0 Register */
#define MCHP_I2SMCC_RHR0R	0x0044	/* Receiver Holding Right 0 Register */

#define MCHP_I2SMCC_RHL1R	0x0048	/* Receiver Holding Left 1 Register */
#define MCHP_I2SMCC_RHR1R	0x004C	/* Receiver Holding Right 1 Register */

#define MCHP_I2SMCC_RHL2R	0x0050	/* Receiver Holding Left 2 Register */
#define MCHP_I2SMCC_RHR2R	0x0054	/* Receiver Holding Right 2 Register */

#define MCHP_I2SMCC_RHL3R	0x0058	/* Receiver Holding Left 3 Register */
#define MCHP_I2SMCC_RHR3R	0x005C	/* Receiver Holding Right 3 Register */

#define MCHP_I2SMCC_THL0R	0x0060	/* Transmitter Holding Left 0 Register */
#define MCHP_I2SMCC_THR0R	0x0064	/* Transmitter Holding Right 0 Register */

#define MCHP_I2SMCC_THL1R	0x0068	/* Transmitter Holding Left 1 Register */
#define MCHP_I2SMCC_THR1R	0x006C	/* Transmitter Holding Right 1 Register */

#define MCHP_I2SMCC_THL2R	0x0070	/* Transmitter Holding Left 2 Register */
#define MCHP_I2SMCC_THR2R	0x0074	/* Transmitter Holding Right 2 Register */

#define MCHP_I2SMCC_THL3R	0x0078	/* Transmitter Holding Left 3 Register */
#define MCHP_I2SMCC_THR3R	0x007C	/* Transmitter Holding Right 3 Register */

#define MCHP_I2SMCC_VERSION	0x00FC	/* Version Register */

/*
 * ---- Control Register (Write-only) ----
 */
#define MCHP_I2SMCC_CR_RXEN		BIT(0)	/* Receiver Enable */
#define MCHP_I2SMCC_CR_RXDIS		BIT(1)	/* Receiver Disable */
#define MCHP_I2SMCC_CR_CKEN		BIT(2)	/* Clock Enable */
#define MCHP_I2SMCC_CR_CKDIS		BIT(3)	/* Clock Disable */
#define MCHP_I2SMCC_CR_TXEN		BIT(4)	/* Transmitter Enable */
#define MCHP_I2SMCC_CR_TXDIS		BIT(5)	/* Transmitter Disable */
#define MCHP_I2SMCC_CR_SWRST		BIT(7)	/* Software Reset */

/*
 * ---- Mode Register A (Read/Write) ----
 */
#define MCHP_I2SMCC_MRA_MODE_MASK		GENMASK(0, 0)
#define MCHP_I2SMCC_MRA_MODE_SLAVE		(0 << 0)
#define MCHP_I2SMCC_MRA_MODE_MASTER		(1 << 0)

#define MCHP_I2SMCC_MRA_DATALENGTH_MASK			GENMASK(3, 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_32_BITS		(0 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_24_BITS		(1 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_20_BITS		(2 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_18_BITS		(3 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS		(4 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS_COMPACT	(5 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS		(6 << 1)
#define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT	(7 << 1)

#define MCHP_I2SMCC_MRA_WIRECFG_MASK		GENMASK(5, 4)
#define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0	(0 << 4)
#define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1	(1 << 4)
#define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2	(2 << 4)
#define MCHP_I2SMCC_MRA_WIRECFG_TDM_3		(3 << 4)

#define MCHP_I2SMCC_MRA_FORMAT_MASK		GENMASK(7, 6)
#define MCHP_I2SMCC_MRA_FORMAT_I2S		(0 << 6)
#define MCHP_I2SMCC_MRA_FORMAT_LJ		(1 << 6) /* Left Justified */
#define MCHP_I2SMCC_MRA_FORMAT_TDM		(2 << 6)
#define MCHP_I2SMCC_MRA_FORMAT_TDMLJ		(3 << 6)

/* Transmitter uses one DMA channel ... */
/* Left audio samples duplicated to right audio channel */
#define MCHP_I2SMCC_MRA_RXMONO			BIT(8)

/* I2SDO output of I2SC is internally connected to I2SDI input */
#define MCHP_I2SMCC_MRA_RXLOOP			BIT(9)

/* Receiver uses one DMA channel ... */
/* Left audio samples duplicated to right audio channel */
#define MCHP_I2SMCC_MRA_TXMONO			BIT(10)

/* x sample transmitted when underrun */
#define MCHP_I2SMCC_MRA_TXSAME_ZERO		(0 << 11) /* Zero sample */
#define MCHP_I2SMCC_MRA_TXSAME_PREVIOUS		(1 << 11) /* Previous sample */

/* select between peripheral clock and generated clock */
#define MCHP_I2SMCC_MRA_SRCCLK_PCLK		(0 << 12)
#define MCHP_I2SMCC_MRA_SRCCLK_GCLK		(1 << 12)

/* Number of TDM Channels - 1 */
#define MCHP_I2SMCC_MRA_NBCHAN_MASK		GENMASK(15, 13)
#define MCHP_I2SMCC_MRA_NBCHAN(ch) \
	((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)

/* Selected Clock to I2SMCC Master Clock ratio */
#define MCHP_I2SMCC_MRA_IMCKDIV_MASK		GENMASK(21, 16)
#define MCHP_I2SMCC_MRA_IMCKDIV(div) \
	(((div) << 16) & MCHP_I2SMCC_MRA_IMCKDIV_MASK)

/* TDM Frame Synchronization */
#define MCHP_I2SMCC_MRA_TDMFS_MASK		GENMASK(23, 22)
#define MCHP_I2SMCC_MRA_TDMFS_SLOT		(0 << 22)
#define MCHP_I2SMCC_MRA_TDMFS_HALF		(1 << 22)
#define MCHP_I2SMCC_MRA_TDMFS_BIT		(2 << 22)

/* Selected Clock to I2SMC Serial Clock ratio */
#define MCHP_I2SMCC_MRA_ISCKDIV_MASK		GENMASK(29, 24)
#define MCHP_I2SMCC_MRA_ISCKDIV(div) \
	(((div) << 24) & MCHP_I2SMCC_MRA_ISCKDIV_MASK)

/* Master Clock mode */
#define MCHP_I2SMCC_MRA_IMCKMODE_MASK		GENMASK(30, 30)
/* 0: No master clock generated*/
#define MCHP_I2SMCC_MRA_IMCKMODE_NONE		(0 << 30)
/* 1: master clock generated (internally generated clock drives I2SMCK pin) */
#define MCHP_I2SMCC_MRA_IMCKMODE_GEN		(1 << 30)

/* Slot Width */
/* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
/* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
#define MCHP_I2SMCC_MRA_IWS			BIT(31)

/*
 * ---- Mode Register B (Read/Write) ----
 */
/* all enabled I2S left channels are filled first, then I2S right channels */
#define MCHP_I2SMCC_MRB_CRAMODE_LEFT_FIRST	(0 << 0)
/*
 * an enabled I2S left channel is filled, then the corresponding right
 * channel, until all channels are filled
 */
#define MCHP_I2SMCC_MRB_CRAMODE_REGULAR		(1 << 0)

#define MCHP_I2SMCC_MRB_FIFOEN			BIT(1)

#define MCHP_I2SMCC_MRB_DMACHUNK_MASK		GENMASK(9, 8)
#define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
	(((fls(no_words) - 1) << 8) & MCHP_I2SMCC_MRB_DMACHUNK_MASK)

#define MCHP_I2SMCC_MRB_CLKSEL_MASK		GENMASK(16, 16)
#define MCHP_I2SMCC_MRB_CLKSEL_EXT		(0 << 16)
#define MCHP_I2SMCC_MRB_CLKSEL_INT		(1 << 16)

/*
 * ---- Status Registers (Read-only) ----
 */
#define MCHP_I2SMCC_SR_RXEN		BIT(0)	/* Receiver Enabled */
#define MCHP_I2SMCC_SR_TXEN		BIT(4)	/* Transmitter Enabled */

/*
 * ---- Interrupt Enable/Disable/Mask/Status Registers A ----
 */
#define MCHP_I2SMCC_INT_TXRDY_MASK(ch)		GENMASK((ch) - 1, 0)
#define MCHP_I2SMCC_INT_TXRDYCH(ch)		BIT(ch)
#define MCHP_I2SMCC_INT_TXUNF_MASK(ch)		GENMASK((ch) + 7, 8)
#define MCHP_I2SMCC_INT_TXUNFCH(ch)		BIT((ch) + 8)
#define MCHP_I2SMCC_INT_RXRDY_MASK(ch)		GENMASK((ch) + 15, 16)
#define MCHP_I2SMCC_INT_RXRDYCH(ch)		BIT((ch) + 16)
#define MCHP_I2SMCC_INT_RXOVF_MASK(ch)		GENMASK((ch) + 23, 24)
#define MCHP_I2SMCC_INT_RXOVFCH(ch)		BIT((ch) + 24)

/*
 * ---- Interrupt Enable/Disable/Mask/Status Registers B ----
 */
#define MCHP_I2SMCC_INT_WERR			BIT(0)
#define MCHP_I2SMCC_INT_TXFFRDY			BIT(8)
#define MCHP_I2SMCC_INT_TXFFEMP			BIT(9)
#define MCHP_I2SMCC_INT_RXFFRDY			BIT(12)
#define MCHP_I2SMCC_INT_RXFFFUL			BIT(13)

/*
 * ---- Version Register (Read-only) ----
 */
#define MCHP_I2SMCC_VERSION_MASK		GENMASK(11, 0)

#define MCHP_I2SMCC_MAX_CHANNELS		8
#define MCHP_I2MCC_TDM_SLOT_WIDTH		32

static const struct regmap_config mchp_i2s_mcc_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = MCHP_I2SMCC_VERSION,
};

struct mchp_i2s_mcc_dev {
	struct wait_queue_head			wq_txrdy;
	struct wait_queue_head			wq_rxrdy;
	struct device				*dev;
	struct regmap				*regmap;
	struct clk				*pclk;
	struct clk				*gclk;
	struct snd_dmaengine_dai_dma_data	playback;
	struct snd_dmaengine_dai_dma_data	capture;
	unsigned int				fmt;
	unsigned int				sysclk;
	unsigned int				frame_length;
	int					tdm_slots;
	int					channels;
	unsigned int				gclk_use:1;
	unsigned int				gclk_running:1;
	unsigned int				tx_rdy:1;
	unsigned int				rx_rdy:1;
};

static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
{
	struct mchp_i2s_mcc_dev *dev = dev_id;
	u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;
	irqreturn_t ret = IRQ_NONE;

	regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
	regmap_read(dev->regmap, MCHP_I2SMCC_ISRA, &sra);
	pendinga = imra & sra;

	regmap_read(dev->regmap, MCHP_I2SMCC_IMRB, &imrb);
	regmap_read(dev->regmap, MCHP_I2SMCC_ISRB, &srb);
	pendingb = imrb & srb;

	if (!pendinga && !pendingb)
		return IRQ_NONE;

	/*
	 * Tx/Rx ready interrupts are enabled when stopping only, to assure
	 * availability and to disable clocks if necessary
	 */
	idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
			    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
	if (idra)
		ret = IRQ_HANDLED