path: root/tools/perf/pmu-events/arch/x86/alderlake/cache.json

[
    {
        "BriefDescription": "L1D.HWPF_MISS",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.HWPF_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALLS",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "UMask": "0x1f",
        "Unit": "cpu_core"
    },
    {