path: root/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json

[
    {
        "BriefDescription": "C10 residency percent per package",
        "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C10_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C1 residency percent per core",
        "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C1_Core_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C2 residency percent per package",
        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C2_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C3 residency percent per package",
        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C3_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C6 residency percent per core",
        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C6_Core_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C6 residency percent per package",
        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C6_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C7 residency percent per core",
        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C7_Core_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C7 residency percent per package",
        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C7_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C8 residency percent per package",
        "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C8_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C9 residency percent per package",
        "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C9_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
        "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
        "MetricGroup": "smi",
        "MetricName": "smi_cycles",
        "MetricThreshold": "smi_cycles > 0.1",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Number of SMI interrupts.",
        "MetricExpr": "msr@smi@",
        "MetricGroup": "smi",
        "MetricName": "smi_num",
        "ScaleUnit": "1SMI#"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions",
        "MetricExpr": "tma_core_bound",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
        "MetricName": "tma_allocation_restriction",
        "MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_backend_bound",
        "MetricThreshold": "tma_backend_bound > 0.1",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "(5 * CPU_CLK_UNHALTED.CORE - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_bad_speculation",
        "MetricThreshold": "tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
        "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_branch_detect",
        "MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts",
        "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
        "MetricName": "tma_branch_mispredicts",
        "MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
        "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_branch_resteer",
        "MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).",
        "MetricExpr": "TOPDOWN_FE_BOUND.CISC / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
        "MetricName": "tma_cisc",
        "MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation",
        "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
        "MetricName": "tma_core_bound",
        "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.",
        "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
        "MetricName": "tma_decode",
        "MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming",
        "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
        "MetricName": "tma_fast_nuke",
        "MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_frontend_bound",
        "MetricThreshold": "tma_frontend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.",
        "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_icache_misses",
        "MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
        "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
        "MetricName": "tma_ifetch_bandwidth",
        "MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.",
        "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
        "MetricName": "tma_ifetch_latency",
        "MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss",
        "MetricExpr": "100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET) / CPU_CLK_UNHALTED.CORE",
        "MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles"
    },
    {
        "BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss",
        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH / CPU_CLK_UNHALTED.CORE",
        "MetricGroup": "Ifetch",
        "MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles",
        "PublicDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound"
    },
    {
        "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
        "MetricExpr": "100 * MEM_BOUND_STALLS.LOAD / CPU_CLK_UNHALTED.CORE",
        "MetricGroup": "Load_Store_Miss",
        "MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles",
        "PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound"
    },
    {
        "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall",
        "MetricExpr": "100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE",
        "MetricGroup": "Mem_Exec",
        "MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles",
        "PublicDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound"
    },
    {
        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricName": "tma_info_br_inst_mix_ipbranch"
    },
    {
        "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL",
        "MetricName": "tma_info_br_inst_mix_ipcall"
    },
    {
        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
        "MetricExpr": &q