path: root/tools/perf/pmu-events/arch/x86/ivytown/cache.json

[
    {
        "BriefDescription": "L1D data line replacements",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "L1D miss outstanding duration in cycles",
        "Counter": "2",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.ALL",
        "SampleAfterValue": "200003",
        "UMask": "0xf"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.HIT_E",
        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.HIT_M",
        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
        "SampleAfterValue": "200003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.MISS",
        "PublicDescription": "Not rejected writebacks that missed LLC.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "L2 cache lines filling L2.",
        "SampleAfterValue": "100003",
        "UMask": "0x7"
    },
    {
        "BriefDescription": "L2 cache lines in E state filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.E",
        "PublicDescription": "L2 cache lines in E state filling L2.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "L2 cache lines in I state filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.I",
        "PublicDescription": "L2 cache lines in I state filling L2.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "L2 cache lines in S state filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.S",
        "PublicDescription": "L2 cache lines in S state filling L2.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Clean L2 cache lines evicted by demand",
        "Counter": "0,1,2,3",
        "EventCode": "0xF2",
        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
        "PublicDescription": "Clean L2 cache lines evicted by demand.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Dirty L2 cache lines evicted by demand",
        "Counter": "0,1,2,3",
        "EventCode": "0xF2",
        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Dirty L2 cache lines filling the L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF2",
        "EventName": "L2_LINES_OUT.DIRTY_ALL",
        "PublicDescription": "Dirty L2 cache lines filling the L2.",
        "SampleAfterValue": "100003",
        "UMask":