path: root/tools/perf/pmu-events/arch/x86/jaketown/cache.json

[
    {
        "BriefDescription": "Allocated L1D data cache lines in M state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.ALLOCATED_IN_M",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.ALL_M_REPLACEMENT",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.EVICTION",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "L1D data line replacements.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0xBF",
        "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
        "SampleAfterValue": "100003",
        "UMask": "0x5"
    },
    {
        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "L1D miss outstanding duration in cycles.",
        "Counter": "2",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.ALL",
        "SampleAfterValue": "200003",
        "UMask": "0xf"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.HIT_E",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.HIT_M",
        "SampleAfterValue": "200003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.HIT_S",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "L2_L1D_WB_RQSTS.MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "L2 cache lines filling L2.",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
        "SampleAfterValue": "100003",
        "UMask": "0x7"
    },
    {
        "BriefDescription": "L2 cache lines in E state filling L2.",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.E",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "L2 cache lines in I state filling L2.",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.I",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "L2 cache lines in S state filling L2.",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.S",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDes