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| author | Imre Deak <imre.deak@intel.com> | 2024-02-20 23:18:30 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2024-02-27 17:34:36 +0200 |
| commit | a4ea61b7482f56cc99391ccf65f13dec2ec51d1d (patch) | |
| tree | 3028a2e5015eac2be1112ed84b8ffb60029462dc /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | 363c31787344f240b7cef68ec2734665ec292f7e (diff) | |
| download | linux-a4ea61b7482f56cc99391ccf65f13dec2ec51d1d.tar.gz linux-a4ea61b7482f56cc99391ccf65f13dec2ec51d1d.tar.bz2 linux-a4ea61b7482f56cc99391ccf65f13dec2ec51d1d.zip | |
drm/i915/dp: Add intel_dp_max_link_data_rate()
Add intel_dp_max_link_data_rate() to get the link BW vs. the sink DPRX
BW used by a follow-up patch enabling the DP tunnel BW allocation mode.
The link BW can be below the DPRX BW due to a BW limitation on a link
shared by multiple sinks.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240220211841.448846-11-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b4d4bb90126e..4b6c8ff97429 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1299,7 +1299,8 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); - max_rate = drm_dp_max_dprx_data_rate(max_link_clock, max_lanes); + max_rate = intel_dp_max_link_data_rate(intel_dp, + max_link_clock, max_lanes); mode_rate = intel_dp_link_required(mode->clock, min_bpp); ret = drm_modeset_lock(&mgr->base.lock, ctx); |