diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-03-31 13:57:35 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-04-07 11:05:47 -0700 |
| commit | 36c5dde5fdf028daf005197a4dd08b196784bf9e (patch) | |
| tree | eeb0fa41956d40edb7db3780456e6426a96e7566 /drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | |
| parent | 6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d (diff) | |
| download | linux-36c5dde5fdf028daf005197a4dd08b196784bf9e.tar.gz linux-36c5dde5fdf028daf005197a4dd08b196784bf9e.tar.bz2 linux-36c5dde5fdf028daf005197a4dd08b196784bf9e.zip | |
drm/msm/dsi: stop passing src_pll_id to the phy_enable call
Phy driver already knows the source PLL id basing on the set usecase and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a slave
mode, so PLL 0 is always a clocksource for DSI 0 and it is always a
clocksource for DSI 1 too unless DSI 1 is used in the standalone mode.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-25-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index f5b88c85a8fc..e96d789aea18 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -63,7 +63,7 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); } -static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, +static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_clk_request *clk_req) { struct msm_dsi_dphy_timing *timing = &phy->timing; @@ -85,7 +85,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); - if (src_pll_id == DSI_1) + if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE) val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; else val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; |