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path: root/drivers/clk/mediatek/clk-pll.c
AgeCommit message (Expand)AuthorFilesLines
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-04-11clk: mediatek: Allow changing PLL rate when it is offJames Liao1-11/+2
2019-04-11clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu1-6/+11
2019-04-11clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen1-4/+11
2019-04-11clk: mediatek: Disable tuner_en before change PLL rateOwen Chen1-14/+34
2017-11-02clk: mediatek: add the option for determining PLL source clockChen Zhong1-1/+4
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com1-2/+11
2016-11-08clk: mediatek: Add MT2701 clock supportShunli Wang1-0/+1
2016-08-18clk: mediatek: remove __init from clk registration functionsJames Liao1-1/+1
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao1-6/+1
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao1-3/+15
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao1-2/+2
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao1-9/+12
2015-05-19clk: mediatek: Initialize clk_init_dataRicky Liang1-1/+1
2015-05-05clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao1-0/+332
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