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path: root/drivers/gpu/drm/i915/display/intel_display.c
AgeCommit message (Expand)AuthorFilesLines
2024-09-03drm/i915/pps: convert intel_pps.[ch] to struct intel_displayJani Nikula1-1/+1
2024-08-29drm/i915/dsb: Use chained DSBs for LUT programmingVille Syrjälä1-0/+1
2024-08-29drm/i915/dsb: s/dsb/dsb_color_vblank/Ville Syrjälä1-1/+1
2024-08-29drm/i915/dsb: Account for VRR properly in DSB scanline stuffVille Syrjälä1-2/+2
2024-08-23drm/i915/tv: convert to struct intel_displayJani Nikula1-1/+1
2024-08-21drm/i915/display: allow creation of Xe2 ccs framebuffersJuha-Pekka Heikkila1-0/+2
2024-08-12drm/i915/bios: convert to struct intel_displayJani Nikula1-4/+5
2024-08-08drm/i915: Replace double blank with single blank after commaAndi Shyti1-1/+1
2024-08-06drm/i915: Replace BPP_X16_FMT()/ARGS() with FXP_Q4_FMT()/ARGS()Imre Deak1-2/+2
2024-08-06drm/i915: Replace to_bpp_int() with fxp_q4_to_int()Imre Deak1-1/+2
2024-07-12drm/i915: Make vrr_{enabling,disabling}() usable outside intel_display.cVille Syrjälä1-9/+17
2024-06-24drm/i915: Use vblank worker to unpin old legacy cursor fb safelyVille Syrjälä1-0/+3
2024-06-20drm/i915: Pass the whole atomic state to intel_color_prepare_commit()Ville Syrjälä1-5/+3
2024-06-20drm/i915: Add async flip tracepointVille Syrjälä1-2/+2
2024-06-13drm/i915: Factor out function to modeset commit a set of pipesImre Deak1-0/+34
2024-06-12drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondaryStanislav Lisovskiy1-171/+171
2024-06-12drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy1-116/+116
2024-06-11drm/i915/display: Skip Panel Replay on pipe comparison if no active planesJouni Högander1-1/+3
2024-06-11drm/i915: Compute CMRR and calculate vtotalMitul Golani1-0/+1
2024-06-11drm/i915: Define and compute Transcoder CMRR registersMitul Golani1-1/+22
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCYJani Nikula1-2/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula1-3/+6
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N2Jani Nikula1-2/+2
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M2Jani Nikula1-2/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N1Jani Nikula1-2/+2
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M1Jani Nikula1-2/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N2Jani Nikula1-2/+2
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M2Jani Nikula1-2/+4
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N1Jani Nikula1-2/+2
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M1Jani Nikula1-2/+4
2024-06-07drm/i915: pass dev_priv explicitly to CHV_CANVASJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to CHV_BLENDJani Nikula1-1/+2
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_ARB_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANSCONFJani Nikula1-23/+29
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOSJani Nikula1-2/+2
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_CONTROLJani Nikula1-5/+6
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MULTJani Nikula1-2/+2
2024-06-07drm/i915: pass dev_priv explicitly to PIPESRCJani Nikula1-3/+3
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFTJani Nikula1-1/+2
2024-06-07drm/i915: pass dev_priv explicitly to BCLRPATJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VSYNCJani Nikula1-3/+3
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VBLANKJani Nikula1-4/+5
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VTOTALJani Nikula1-5/+5
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HSYNCJani Nikula1-3/+3
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HBLANKJani Nikula1-3/+4
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HTOTALJani Nikula1-3/+3
2024-06-07drm/i915: pass dev_priv explicitly to DPLLJani Nikula1-10/+11
2024-05-31drm/i915: Plumb the full atomic state into icl_check_nv12_planes()Ville Syrjälä1-5/+6
2024-05-30drm/i915/display: Add compare config for MTL+ platformsMika Kahola1-0/+33
2024-05-27drm/i915: Bury c8_planes_changed() in intel_color_check()Ville Syrjälä1-18/+0
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